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d a t a sh eet product speci?cation file under integrated circuits, ic22 2001 jun 19 integrated circuits p83cl882 80c51 ultra low power (ulp) telephony controller
2001 jun 19 2 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 contents 1 features 2 general description 3 ordering information 4 block diagram 5 pinning information 5.1 pin configuration 5.2 pin description 6 functional description 6.1 oscillator circuitry 6.2 the cpu 6.3 interrupt controller 6.4 port control logic 6.5 timer 0 and timer 1 event counters 6.6 timer 2 6.7 watchdog timer 6.8 i 2 c-bus serial i/o (master/slave interface) 6.9 msk modem 6.10 internal data memory 6.11 special function registers overview 7 instruction set 7.1 instruction map 8 application information 8.1 introduction 8.2 differences between p83cl882 and the metalink eh emulation system 8.3 the asynchronous handshake cpu 9 how to estimate p83cl882 power consumption 9.1 general 9.2 modes 9.3 examples of power consumption estimation 10 limiting values 11 characteristics 12 package outline 13 soldering 13.1 introduction to soldering surface mount packages 13.2 reflow soldering 13.3 wave soldering 13.4 manual soldering 13.5 suitability of surface mount ic packages for wave and reflow soldering methods 14 data sheet status 15 definitions 16 disclaimers 17 purchase of philips i 2 c components
2001 jun 19 3 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 1 features full static asynchronous handshake 80c51 cpu; enhanced 8-bit architecture with: C standard 80c51 instruction set C cpu speed independent of clock frequency, average speed: 4.8 mips at 3.0 v C non-page oriented instructions C direct addressing C four 8-byte ram register banks C stack depth limited only by available internal ram (maximum 128 bytes) C multiply, divide, subtract and compare instructions. 17 source, 17 vector interrupt structure with two priority levels, polarity and sensitivity choice 24 general purpose i/o pins timer 0 and 1: two standard 16-bit timer/event counters timer 2: 16-bit timer/event counter with capture, compare and auto-reload function watchdog timer wake-up counter idle and power-down modes 4-kbyte rom: mask programmed read only memory supply voltage: 1.8 to 3.6 v 128 bytes ram internal crystal oscillator reset i/o pin for external reset from master or to slave msk modem including manchester encoder/decoder with 2 digital outputs (by sw) for analog cordless telephones (standards ct0/ct1/ct1+) i 2 c-bus master/slave (transmitter/receiver, maximum frequency 400 khz). 2 general description the p83cl882 is manufactured in an advanced cmos technology. the p83cl882 is a member of the vtelx family of low-power, low-voltage 80cl51 microcontrollers with advanced features for telecom applications. the philips exclusive, asynchronous handshaking technology has been used for the cpu implementation which makes the cpu to run at its maximum speed independent of the used crystal frequency. the p83cl882 is especially suited for low cost analog cordless telephone applications (ct0, ct1 and ct1+ standards) and wired feature phones. for this purpose, functions like msk modem and i 2 c-bus are integrated on-chip. the device is optimized for low-power consumption. it has two software selectable modes for power reduction: idle and power-down. in addition, the clock to all unused peripheral blocks can be switched off. the instruction set is based on that of the 80c51. the p83cl882 also functions as an arithmetic processor having facilities for both binary and bcd arithmetic plus bit-handling capabilities. the instruction set consists of over 100 instructions: 49 one-byte, 46 two-byte, and 16 three-byte. port 2 is not incorporated, therefore there is no external data or memory access and the movx operations cannot be used. 3 ordering information type number package name description version p83cl882t/xxx tssop32 plastic thin shrink small outline package; 32 leads; body width 6.1 mm sot487-1
2001 jun 19 4 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 4 block diagram handbook, full pagewidth mgu258 (2) t0 (2) t1 timer 0 timer 1 rom interrupt control ram internal bus cpu 80c51 rst irst mode selection select xtm mode and test control (2) mout2 to mout0 f per f osc f osc msk modem xtal2 xtal1 amplitude controlled oscillator oscillator comparator block psc2 psc1 min v dd v ss v ddp v ssp port control port 0 port 3 timer 2 i 2 c-bus interface watchdog timer port 1 f psc f per f per f psc f psc sda (1) scl (1) t2out (1) t2ex (1) t2 (1) p3 p1 p0 p83cl882 fig.1 simplified block diagram. (1) alternative function of port 1. (2) alternative function of port 3.
2001 jun 19 5 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 5 pinning information 5.1 pin con?guration handbook, halfpage p83cl882 mgu265 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p3.3 p3.4/t0 p3.5/t1 p3.6 p3.7 p1.2/int4/t2 p1.1/int3/t2ex p1.0/int2 v ss v dd xtal2 xtal1 rst p3.0/mout0 p3.1/int1/mout1 p3.2/int0/mout2 v ssp v ddp p1.5/int7 p1.4/int6/clkout p1.3/int5 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 p1.7/int9/sda p1.6/int8/scl min 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 fig.2 pin configuration (tssop32/sot487-1).
2001 jun 19 6 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 5.2 pin description table 1 pin description for tssop32 (sot487-1) note 1. for high current drive capability on i/os all supply pins should be connected. symbol pin type description p3.3 1 i/o port 3: p3.3 to p3.7; bidirectional i/o port with two alternative functions. p3.4 also serves as the timer 0 external count input (t0). p3.5 also serves as the timer 1 external count input (t1). p3.4/t0 2 i/o p3.5/t1 3 i/o p3.6 4 i/o p3.7 5 i/o p1.2/int4/t2 6 i/o port 1: p1.2 to p1.0; bidirectional i/o port with alternative functions. int4, int3 and int2 are the external interrupts 4, 3 and 2 respectively. p1.2 also serves as timer 2 input (t2). p1.1 also serves as timer 2 external input (t2ex). p1.1/int3/t2ex 7 i/o p1.0/int2 8 i/o v ss (1) 9 s ground v dd (1) 10 s power supply voltage xtal2 11 o crystal output xtal1 12 i crystal input; external clock input rst 13 i/o reset input/output pin; active low p3.0/mout0 14 i/o port 3: p3.0 to p3.2; bidirectional i/o port with alternative functions. mout2 to mout0 are the msk outputs (mapped on the lower 3 bits of port 3). p3.2 also serves as the external interrupt 0 input (int1) and p3.1 as the external interrupt 1 input (int0). p3.1/mout1/int1 15 i/o p3.2/mout2/int0 16 i/o min 17 i msk input p1.6/int8/scl 18 i/o port 1: p1.6 and p1.7; can only be used as open-drain output or high-impedance input. alternative functions: int8 and int9, external interrupt 8 and 9. scl and sda i 2 c-bus interface clock and data. p1.7/int9/sda 19 i/o p0.0 to p0.7 20 to 27 i/o port 0: 8-bit bidirectional i/o port. every port pin can be used as open-drain, standard port, high-impedance input or push-pull output. p1.3/int5 28 i/o port 1: p1.3 to p1.5; bidirectional i/o port with alternative functions int5, int6 and int7: external interrupt 5 to 7. p1.4 also serves as auxiliary clock output (clkout). p1.5 also serves as the timer 2 output (t2out). p1.4/int6/clkout 29 i/o p1.5/int7/t2out 30 i/o v ddp (1) 31 s periphery (i/o) positive supply voltage v ssp (1) 32 s periphery (i/o) ground
2001 jun 19 7 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6 functional description 6.1 oscillator circuitry the on-chip amplitude controlled oscillator (aco) circuitry is a single-stage inverting amplifier biased by an internal feedback resistor r fb . the oscillator circuit is shown in fig.3. two comparators with different characteristics can be used with the on-chip crystal oscillator. the first one is an analog comparator built around a differential amplifier and is intended to be selected when an external ceramic or crystal resonator is connected to the chip. the other comparator has a schmitt trigger input with a bigger hysteresis which is especially useful when the p83cl882 is driven from an external clock source. two bits in the syscon sfr: select and xtm, are used to configure the oscillator. the select bit (syscon.1) enables the analog comparator or the hysteresis comparator. with xtm (syscon.0) = 1 (or in power-down mode; pcon.1 = 1) the oscillator is switched off and the current consumption of the oscillator is reduced to zero. table 2 comparator select bits in syscon sfr 6.1.1 c lock oscillator connections no external components are needed when a quartz crystal is used to drive the oscillator. when an external ceramic resonator is used to drive the oscillator, external components may be required depending upon the ceramic resonator type; refer to the product specification. two different resonator configurations are shown in figs 4a and 4b. to drive the device with an external clock source, apply the external clock signal to xtal1, and leave xtal2 floating, as shown in fig.4c. if the amplitude of the input signal is less than v dd to v ss or if a sine wave is applied, capacitive decoupling is needed as shown in fig.4d. select xtm description 0 0 oscillator enabled; analog comparator enabled 0 1 dont use 1 0 oscillator enabled; hysteresis comparator enabled 1 1 oscillator stopped; hysteresis comparator enabled xtal2 select xtal1 xtm r fb enable enable anacomp enable hystcomp psc1 f psc psc2 f per f osc mgt281 fig.3 oscillator.
2001 jun 19 8 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 handbook, full pagewidth mbh986 xtal1 xtal2 (c) xtal1 xtal2 (d) n.c. n.c. xtal1 xtal2 (b) xtal1 xtal2 (a) standard quartz oscillator oscillator with external capacitors (quartz or pxe) external clock (square) external clock (sine) fig.4 alternative oscillator configurations.
2001 jun 19 9 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.1.2 r esonator requirements for the aco in fig.5a the complete pierce type oscillator is shown, while fig.5b presents the corresponding equivalent circuit used for calculations. at the resonance frequency the behaviour of a crystal resonator can be approximated by its equivalent circuit, as shown in fig.5b. the values of the components r s , l, c s and c o in the crystal equivalent circuit are usually specified in the data sheet of the crystal supplier. the inverting amplifier is replaced by its equivalent circuit, the current source with the transconductance g m and the output impedance r g; as shown in fig.5b. with some calculation the condition below can be found, which estimates a minimal value for g m of the inverter which is required for the oscillation: where and r f is an internal bias resistor, and c f stands for all of the parasitic capacitors parallel to the gate, from input to the output. parasitic capacitors from input or output to ground are included with c 1 or c 2 . the input impedance of a cmos gate is high and can be neglected. it is advised to keep the wiring between chip and resonator as short as possible. g m 4r s w o 2 c p 2 4 r f ----- 1 r g ------ - ++ 3 c p c o c f c e 2 ------ - ++ = c 1 c 2 c e == handbook, halfpage mbl311 c 2 c 1 xtal1 xtal2 - g m handbook, halfpage mbl310 r s r f r g i g = - g m v i c 2 c 1 c f v i xtal1 xtal2 l c s c o a. crystal oscillator. b. crystal oscillator equivalent circuit. fig.5 crystal oscillator and its equivalent circuit.
2001 jun 19 10 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.1.3 o n - chip clocks the microcontroller does not need a clock signal to run instructions, because the cpu is built using the philips exclusive handshake technology. the peripheral blocks however are connected to a clock for synchronization with the outside world (e.g. msk) or for a timed application (e.g. timer 2). the block related sfrs (peripheral function) are therefore updated/modified with the applied clock. two prescalers (psc1 and psc2) are implemented which allow the generation of two programmable clock signals f psc and f per for internal usage. signal f psc from psc1 is the default input clock of the timer blocks. the complete timer functionality is specified in the section 6.5. connected timers are the three 16-bit timers timer 0, 1 and 2 and the 8-bit watchdog timer. the time interval of the connected timers can be adjusted by programming of psc1. the output frequency f psc can be changed by selecting the division factor with the bits presc.[2:0], (see table 7). all peripheral blocks, which require a clock signal: msk, and i 2 c-bus interface are connected to the clock signal f per . psc2 can be programmed by setting bits presc.4 and presc.3 (see table 7). the choice of the division factor must guarantee that all of the peripheral blocks are within their specification, specially if an external clock source of up to 12 mhz is applied. additionally timer 1 and timer 0 have a multiplexer on the clock input to choose from 4 different clock sources. the multiplexers are switched by setting user controllable bits in the syscon sfr (bits 7 to 4). in the default setting both timers are incrementing on the clock signal f psc coming from psc1. timer 1 and timer 0 can however also run on clock signal f per coming from psc2. if used in the proper way this flexibility on the timer input sources can substantially contribute to a decrease in power consumption. ideas and tips to reduce power consumption are given in chapter 9. the clock source of timer 1 and timer 0 can also be switched to an external clock input signal t1 or t0 which are multiplexed with one of the device input pins. this mode is also functional even when there is no system clock available. this means when a clock source is supplied on a port pin timer 1 or timer 0 can count and generate interrupts even when the chip is in power-down mode. more details are specified in section 6.5. the last multiplexer input to timer 1 and timer 0 is an auxiliary mode which can be used to obtain the operation speed from the handshake cpu. if this mode is activated for the timer 1 input source, the timer increments on every rom request. this means the timer increments by three for a three byte instruction and by two for a two byte instruction etc. if the auxiliary mode is activated for timer 0 the timer increments on every instruction executed by the cpu. this means the timer register holds the number of instructions executed in a certain time frame. more ideas and tips on how these clock source modes can be used together with the handshake cpu can be found in chapter 9. table 3 timer 1 input source select modes bits t1src[1:0] are de?ned in syscon sfr. table 4 timer 0 input source select modes bits t0src[1:0] are de?ned in syscon sfr. t1src1 t1src0 description 00f psc is the timer 1 clock input 0 1 t1 is the timer 1 clock input 1 0 the romreq signal is the timer 1 clock input 11f per is the timer 1 clock input t0src1 t0src0 description 00f psc is the timer 0 clock input 0 1 t0 is the timer 0 clock input 1 0 the instrreq signal is the timer 0 clock input 11f per is the timer 0 clock input
2001 jun 19 11 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 handbook, full pagewidth mgu266 watchdog timer timer 2 timer 1 timer 0 oscillator and comparator xtal1 t1src1/t1src0 t0src1/t0src0 xtal2 romreq t1 f psc msk modem i 2 c-bus ports f per f osc f osc f psc instrreq t0 select xtm power-down to pin p1.4 clkout cpu synchronisation auxsw extck sync auxclk fig.6 clock overview.
2001 jun 19 12 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.1.3.1 prescaler register (presc) reset value of presc sfr is xxx0 0000 (division factor 1 for psc1 and psc2). table 5 prescaler register (sfr address f3h) table 6 description of presc bits table 7 division factors for psc1 and psc2 6.1.4 a uxiliary clock signal modes the 3 most significant bits in the prescaler register (see tables 5 and 6) are used to enable additional clocking options. a multiplexer is implemented (see fig.6) to choose between f psc and f per as the source for auxclk. the multiplexer is operated by bit auxsw (presc.6). with bit extck (presc.7) the auxclk is fed to pin p1.4 (clkout) for external use (initialize the port accordingly). setting bit sync (presc.5) connects the auxclk to the instruction request input of the cpu. in this way the cpu is synchronised to the clock and an instruction is executed at every clock pulse of auxclk. in order to obtain exactly one instruction per clock cycle the period for auxclk must always be longer than the length of the slowest instruction. 76543210 extck auxsw sync presc.4 presc.3 presc.2 presc.1 presc.0 bit symbol description 7 extck switches auxclk to device pin p1.4 (clkout). 6 auxsw auxiliary clock switch. if auxsw = 0; then auxclk equals f psc . if auxsw = 1; then auxclk equals f per . 5 sync switches the cpu to synchronous mode. 4 to 0 presc.[4:0] these bits de?ne the division factors for psc1 and psc2; see table 7. division factor presc.4 presc.3 presc.2 presc.1 presc.0 psc2 (f osc /f per ) psc1 (f osc /f psc ) 1 - 0 0xxx 2 - 0 1xxx 4 - 1 0xxx 8 - 1 1xxx - 1xx000 - 2xx001 - 4xx010 - 6xx011 - 8xx100 - 10xx101 - 12xx110 - 16xx111
2001 jun 19 13 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.1.5 s ystem c ontrol r egister (syscon) table 8 system control register (sfr address b4h) table 9 description of syscon bits 76543210 t1src1 t1src0 t0src1 t0src0 -- select xtm bit symbol description 7 t1src1 these 2 bits select the clock source for timer 1; see table 3. 6 t1src0 5 t0src1 these 2 bits select the clock source for timer 0; see table 4. 4 t0src0 3 - do not use 2 1 select comparator select bit; see table 2 0 xtm oscillator disable bit; see table 2
2001 jun 19 14 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.2 the cpu 6.2.1 g eneral ultra low power (ulp), points to the special 80c51 cpu architecture used in this device allowing significant power saving. the cpu of the p83cl882 is realized in the philips exclusive asynchronous handshaking technology, which is completely different to usual implementations of this core. the processor does not need a clock signal to run instructions. every function within the cpu is self timed and always runs at the maximum speed that the silicon die under the current operating conditions allows (supply voltage and temperature). the advantage is the combination of a high computing power with reduced average power consumption and low emc noise generation. details about speed and energy consumption per instruction can be found in chapter 8. summary of the cpu features: no cpu clock is needed only useful bytes are fetched from the program memory; the dummy read cycles which exist in the standard 80c51 have been eliminated to save power to further speed up the program execution; there is always a pre-fetch of the next byte of code from memory during the execution of the current instruction; in the case of a jump the pre-fetched byte is discarded in idle mode the cpu power is reduced to leakage; only the enabled peripheral blocks consume power but can be switched off independently the only need for a clock is as a timing reference for timers/counters and to generate the timing for the i/o lines to synchronise with the off-chip world. 6.2.2 r eset operation there are two possibilities to reset the cpu (see fig.7): watchdog timer reset external reset via i/o pin rst. if an internal reset is executed (watchdog timer), the reset pin rst will be pulled to ground which can be used as reset signal for other ics. the reset pin is low for at least 1024 clock cycles, and released 16 clock cycles prior to first code fetch (see figs 8 and 9). handbook, full pagewidth internal reset watchdog timer r pu v ss v dd rst (external reset) logic mgu267 fig.7 reset sources.
2001 jun 19 15 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.2.2.1 watchdog timer reset if the watchdog timer expires, it will trigger a reset. mgt287 watchdog timer 1024 clocks 16 clocks cpu start rst output cpu activity fig.8 watchdog timer reset timing.
2001 jun 19 16 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.2.2.2 external reset via rst an external device can cause a chip reset, if the reset pin rst is pulled to ground. mgt546 rst by counter maximum 16384 = 2 14 clocks 16 clocks 8 clocks rst cpu activity external applied mgt286 rst by counter maximum 16384 = 2 14 clocks 16 clocks 8 clocks rst cpu activity minimum 8 clocks external applied fig.9 external reset. a. short external reset. b. long external reset.
2001 jun 19 17 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.2.3 i dle and p ower - down operation idle and power-down are power saving modes of the microcontroller that can be activated when no cpu activity is required. these two modes are extremely useful for the asynchronous cpu, because they offer the possibility to profit from the speed of the cpu and to save power as soon as the task is finished. idle mode stops the code execution of the cpu, but the internal oscillator remains active, and also all peripheral functions connected to the on-chip clock signal. unused blocks can be switched off independently. however, during power-down mode the clock oscillator is stopped and therefore also all peripheral blocks will stop their activity. 6.2.3.1 idle mode the following functions remain active during idle mode: timers 0, 1 and 2 wake-up counter watchdog timer counter msk modem i 2 c-bus interface external interrupt. the instruction that sets pcon.0 (pcon sfr) is the last instruction executed in the normal operating mode before the idle mode is activated. the ram and all of the registers are preserved and maintain their data during idle mode: the cpu status, the stack pointer, program counter, program status word and accumulator. there are two ways to terminate the idle mode: activation of any enabled interrupt will cause pcon.0 to be cleared by hardware thus terminating the idle mode. the interrupt is serviced, and following the reti instruction, the next instruction to be executed will be the one following the instruction that put the device in the idle mode. the second way of terminating the idle mode is with an internal or external hardware reset. reset redefines all sfrs but does not affect the on-chip ram. the source of an internal reset is the watchdog timer if the preset delay has expired. 6.2.3.2 power-down mode the instruction that sets pcon.1 (pcon sfr) is the last instruction executed in the normal operating mode before the power-down mode is activated. during power-down mode, the ram and all of the registers maintain their data: the cpu status, the stack pointer, program counter, program status word and accumulator. there are two ways to terminate the power-down mode: activation of any of the interrupts listed below will cause pcon.1 to be cleared by hardware thus terminating the power-down mode. the interrupt is serviced, and following the reti instruction, the next instruction to be executed will be the one following the instruction that put the device in the power-down mode. interrupts which can generate a wake-up from power-down: C external interrupts (int0 to int9) C timer 0 and timer 1: only when pins t0 and t1 are used as the external timer source input (syscon sfr bits 7 to 4) the second way of terminating the power-down mode is with an internal or external hardware reset. reset does not affect the on-chip ram, but all sfrs are set to the default value.
2001 jun 19 18 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.2.3.3 power control register (pcon) the reduced power modes are activated by software using this special function register. pcon is not bit addressable. the reset value of pcon = 0000 0000. table 10 power control register (sfr address 87h) bits pcon[7:2] are reserved and must be kept to logic 0. table 11 reduced power modes selection 6.2.4 cpu start - up timing 6.2.4.1 cpu start-up after reset three possibilities on how the cpu can start executing code after a reset phase are described below. when the cpu is triggered to wake-up after a power-on reset (see fig.8), the clock oscillator usually needs some time to ramp up. to allow the oscillator to stabilize the cpu contains a down counter for a fixed delay of 1024 + 16 clock cycles. after this delay the cpu starts with code execution. when cpu start-up is initiated from an external reset (see fig.9), the down counter is not initialized and the time between reset going active and first code execution can be maximum 16400 clock cycles. when a cpu start-up is after a watchdog timer reset (see fig.8), the rst pin will be pulled low for 1024 clock cycles. another 16 clocks later the cpu will start executing code. 6.2.4.2 cpu start-up after power-down after wake-up from power-down mode (see fig.10) the user has the possibility to shorten the start-up time by programming the wake-up counter register (wkcon). this can be useful when an external clock source is used instead of the on-chip oscillator, or when the accuracy of the time reference is not needed immediately after a restart. this feature enables power saving and fast wake-up in applications where the cpu frequently goes into power-down mode. the wake-up delay can be calculated as shown in table 13. 76543210 000000pdidl pd idl description 0 0 cpu running 0 1 activates the idle mode 1 0 activates the power-down mode 11
2001 jun 19 19 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.2.5 w ake - up c ounter r egister (wkcon) table 12 wake-up counter register (sfr address ddh) table 13 description of wkcon bits 76543210 wkcon.7 wkcon.6 wkcon.5 wkcon.4 wkcon.3 wkcon.2 wkcon.1 wkcon.0 bit symbol description 7 to 0 wkcon.[7:0] the wake-up delay can be calculated as follows: wake-up delay = (1024 - 4) wkcon. where wkcon is the content of the wake-up counter register. wkcon = 00h: (default) wake-up delay = 1024 clocks wkcon = cch: wake-up delay = 208 clocks wkcon = ffh: wake-up delay = 4 clocks. mgt288 wake-up event programmable delay oscillator stop cpu activity cpu start clock cpu stop start unstable clock fig.10 wake-up timing from power-down.
2001 jun 19 20 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.3 interrupt controller in order to service interrupt requests coming from external events and from the on-chip peripherals the p83cl882 offers a 17 source, two priority level nested interrupt system. a detailed description of the interrupt process is given in the following sections. table 14 shows the available interrupts with each vector address and table 15 shows an overview of all the interrupt related sfrs. the detailed interrupt related sfr description can be found in sections 6.3.4 to 6.3.10. 6.3.1 g eneral each interrupt vector points to a separate location in program memory for its service routine. each source can be individually enabled or disabled by its corresponding bit in the interrupt enable registers (ien0, ien1 and ien2). the priority level is selected via the interrupt priority registers (ip0, ip1 and ip2). all available interrupts can be globally disabled or enabled. the interrupt controller samples all active sources during one instruction cycle. evaluation of the interrupts is then performed. a priority decoder decides which interrupt is serviced. each interrupt has its own vector pointing to an 8 bytes long memory segment. a low priority interrupt can be interrupted by a high priority interrupt, but not by another low priority interrupt i.e. only two interrupt levels are possible. between the reti instruction (return from interrupt) and the execution of a next interrupt at least one instruction of the lower program level is executed. the interrupt service with different priorities is shown in fig.11. an interrupt is performed with a long subroutine call (lcall) to a vector address, which is determined by the respective interrupt. during lcall the program counter (pc) is pushed onto the stack. returning from interrupt with reti, the pc is popped from the stack. in the event of several interrupts with the same priority level, the order of sequence in which they will be serviced is determined by the scanning order. the interrupt highest in the scanning list will always be served first, interrupts lower in the scanning list will be served in the order as shown in fig.12. no interrupt will be lost. table 14 available interrupts (ordered by vector address) hw = hardware; sw = software. source symbol vector (hex) cleared by int 0 x0 0003 hw timer 0 t0 000b hw int 1 x1 0013 hw timer 1 t1 001b hw i 2 c-bus s1 002b sw timer 2 t2 0033 sw int2 x2 003b sw int3 x3 0043 sw int4 x4 004b sw int5 x5 0053 sw int6 x6 005b sw int7 x7 0063 sw int8 x8 006b sw int9 x9 0073 sw msk modem transmitter mti 0083 sw msk mode receiver mri 008b sw watchdog timer wdi 00b3 sw
2001 jun 19 21 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 table 15 interrupt related sfrs sfr description sfr address reset value ien0 interrupt enable register 0 a8h 0000 0000 ien1 interrupt enable register 1 (int2 to int9) e8h 0000 0000 ien2 interrupt enable register 2 f1h 0000 0000 ip0 interrupt priority register 0 b8h 0000 0000 ip1 interrupt priority register 1 (int2 to int9) f8h 0000 0000 ip2 interrupt priority register 2 f9h 0000 0000 ix1 external interrupt polarity register 1 e9h 0000 0000 ise1 external interrupt sensitivity register 1 e1h 0000 0000 irq1 external interrupt request ?ag register 1 c0h 0000 0000 handbook, full pagewidth mgr125 interrupt level 2x interrupt level 1 program level 0 reti level 21 reti level 20 reti one instruction ip = 1 ip = 1 ip = 0 fig.11 interrupt hierarchy.
2001 jun 19 22 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 x0 x5 mri t0 t2 s1 x6 mti x1 x2 x7 t1 x3 x8 x4 x9 wdi ien0 ien1 ien2 ip0 ip1 ip2 interrupt sources decreasing priority within same level high low mgu259 fig.12 interrupt assignment and priorities (listed by scanning order).
2001 jun 19 23 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.3.2 i nterrupt process 1. sample the interrupt lines. the interrupt lines are latched at the beginning of each instruction cycle. 2. analyse the requests. the sampled interrupt lines will be analysed with respect to the relevant interrupt enable register (ienx) and interrupt priority register (ipx). the process will deliver the vector of the highest interrupt request and the priority information. depending on the interrupt level and the priority of the interrupt in progress, an interrupt request to the core is performed. the vector address will be passed to the core process. 3. interrupt request to core. a) level 0: the interrupt request to the core is performed, when at least one instruction is performed since the reti from level 1. b) level 1: the interrupt request is performed, when at least one instruction is performed since the reti from level 21 and the request has high priority. c) level 20: no request is performed. d) level 21: no request is performed. 4. update the interrupt level. a) level 0: in the event of a high priority interrupt the new level will be level 20; if it is a low priority interrupt, the new level will be level 1. b) level 1: in the event of a high priority interrupt, the new level will be level 21; a low priority interrupt is not performed, the level is unchanged; on reti the new level will be level 0. c) level 20: on reti; the new level is level 0. d) level 21: on reti; the new level is level 1. e) level 1: on reti; the new level is level 0. f) level 0: the new level is level 0. 5. clearing the flags. during the forced lcall the interrupt flag of the relevant interrupt is cleared by hardware, if applicable, otherwise by software. 6. idle and power-down. when idle (pcon.0) or power-down (pcon.1) is set, the interrupt controller waits for the wake-up signal. because the interrupt controller is waiting for wake-up, all activity in the circuit will be stopped, thus no handshake can be completed. the wake-up signal for idle is the or of all the interrupt request bits and the reset. for power-down the wake-up signal is built only with the port 1 external interrupt request flags (x2 to x9) and the reset (external reset). 6.3.3 p ort 1 interrupts eight port 1 lines can be used as external interrupt inputs (x2 to x9). when enabled by ien1 sfr, each of these interrupts may wake-up the device from idle or power-down. these external interrupts can each independently be programmed to positive and negative polarity and to edge and level sensitivity by setting sfr ix1 and ise1 (see table 34). figure 12 shows programming of polarity and sensitivity of the port 1 interrupts. when a valid event occurs on an enabled port 1 interrupt, the corresponding bit in the interrupt request flags register will be set (irq1). the interrupt request flags must be cleared by software.
2001 jun 19 24 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.3.4 i nterrupt e nable r egister 0 (ien0) table 16 interrupt enable register 0 (sfr address a8h) table 17 description of ien0 bits logic 0 = interrupt disabled; logic 1 = interrupt enabled. 6.3.5 i nterrupt e nable r egister 1 (ien1) table 18 interrupt enable register 1 (sfr address e8h) table 19 description of ien1 bits logic 0 = interrupt disabled; logic 1 = interrupt enabled. 76543210 ea et2 es1 - et1 ex1 et0 ex0 bit symbol description 7ea general enable/disable control. if ea = 0, no interrupt is enabled; if ea = 1, any individually enabled interrupt will be accepted. 6 et2 enable t2 interrupt 5 es1 enable i 2 c-bus interrupt 4 - reserved 3 et1 enable timer 1 interrupt (t1) 2 ex1 enable external interrupt 1 1 et0 enable timer 0 interrupt (t0) 0 ex0 enable external interrupt 0 76543210 ex9 ex8 ex7 ex6 ex5 ex4 ex3 ex2 bit symbol description 7 ex9 enable external interrupt 9 6 ex8 enable external interrupt 8 5 ex7 enable external interrupt 7 4 ex6 enable external interrupt 6 3 ex5 enable external interrupt 5 2 ex4 enable external interrupt 4 1 ex3 enable external interrupt 3 0 ex2 enable external interrupt 2
2001 jun 19 25 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.3.6 i nterrupt e nable r egister 2 (ien2) table 20 interrupt enable register 2 (sfr address f1h) table 21 description of ien2 bits logic 0 = interrupt disabled; logic 1 = interrupt enabled. 6.3.7 i nterrupt p riority r egister 0 (ip0) table 22 interrupt priority register 0 (sfr address b8h) table 23 description of ip0 bits logic 0 = low priority; logic 1 = high priority. 76543210 ewdi ----- emti emri bit symbol description 7 ewdi enable watchdog timer interrupt 6 - reserved 5 - reserved 4 - reserved 3 - reserved 2 - reserved 1 emti enable msk transmitter interrupt 0 emri enable msk receiver interrupts 76543210 - pt2 ps1 - pt1 px1 pt0 px0 bit symbol description 7 - reserved 6 pt2 timer 2 interrupt priority level 5 ps1 i 2 c-bus interrupt priority level 4 - reserved 3 pt1 timer 1 interrupt priority level 2 px1 external interrupt 1 priority level 1 pt0 timer 0 interrupt priority level 0 px0 external interrupt 0 priority level
2001 jun 19 26 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.3.8 i nterrupt p riority r egister 1 (ip1) table 24 interrupt priority register 1 (sfr address f8h) table 25 description of ip1 bits logic 0 = low priority; logic 1 = high priority. 6.3.9 i nterrupt p riority r egister 2 (ip2) table 26 interrupt priority register 2 (sfr address f9h) table 27 description of ip2 bits logic 0 = low priority; logic 1 = high priority. 76543210 px9 px8 px7 px6 px5 px4 px3 px2 bit symbol description 7 px9 external interrupt 9 priority level 6 px8 external interrupt 8 priority level 5 px7 external interrupt 7 priority level 4 px6 external interrupt 6 priority level 3 px5 external interrupt 5 priority level 2 px4 external interrupt 4 priority level 1 px3 external interrupt 3 priority level 0 px2 external interrupt 2 priority level 76543210 pwdi ----- pmti pmri bit symbol description 7 pwdi watchdog timer interrupt priority level 6 - reserved 5 - reserved 4 - reserved 3 - reserved 2 - reserved 1 pmti msk transmitter interrupt priority level 0 pmri msk receiver interrupt priority level
2001 jun 19 27 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.3.10 i nterrupt r equest f lag r egister 1 (irq1) table 28 interrupt request flag register 1 (sfr address c0h) table 29 description of irq1 bits 6.3.11 i nterrupt polarity and s ensitivity registers 6.3.11.1 interrupt polarity register 1 (ix1) writing either a logic 1 or logic 0 to any interrupt polarity register bit sets the polarity of the corresponding external interrupt. if the interrupt sensitivity bit (ise1 register, section 6.3.11.2) is set to level sensitive then a logic 1 corresponds to active high level and logic 0 to active low level. if the ise1 register is set to edge sensitive then a logic 1 corresponds to a rising edge and a logic 0 to a falling edge. see also table 34 and fig.12. table 30 interrupt polarity register 1 (sfr address e9h) table 31 description of ix1 bits 76543210 iq9 iq8 iq7 iq6 iq5 iq4 iq3 iq2 bit symbol description 7 iq9 external interrupt 9 request ?ag 6 iq8 external interrupt 8 request ?ag 5 iq7 external interrupt 7 request ?ag 4 iq6 external interrupt 6 request ?ag 3 iq5 external interrupt 5 request ?ag 2 iq4 external interrupt 4 request ?ag 1 iq3 external interrupt 3 request ?ag 0 iq2 external interrupt 2 request ?ag 76543210 ix9 ix8 ix7 ix6 ix5 ix4 ix3 ix2 bit symbol description 7 to 0 ix9 to ix2 external interrupt 9 to 2 polarity level
2001 jun 19 28 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.3.11.2 interrupt sensitivity register 1 (ise1) writing either a logic 1 or logic 0 to an interrupt sensitivity register bit sets the type of the corresponding external interrupt to edge sensitive (logic 1) or level sensitive (logic 0). table 32 interrupt sensitivity register 1 (sfr address e1h) table 33 description of ise1 bits 6.3.11.3 interrupt polarity and sensitivity options table 34 interrupt polarity and sensitivity options n denotes the bit position in the sfrs ix1 and ise1. 76543210 ise9 ise8 ise7 ise6 ise5 ise4 ise3 ise2 bit symbol description 7 to 0 ise9 to ise2 external interrupt 9 to 2 sensitivity ix1.n ise1.n description 0 0 low-level sensitive 1 0 high-level sensitive 0 1 falling edge sensitive 1 1 rising edge sensitive mgt290 p1.n port1 ise1.n ix1.n negative level positive edge irq1.n ien1.n positive level negative edge fig.13 polarity and sensitivity of port 1 interrupts.
2001 jun 19 29 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.4 port control logic four 8-bit i/o ports are implemented in the device. some of these general purpose i/os are multiplexed with alternative functions. port 0 is the only port with no multiplexed alternative functions. port 3 and a part of port 1 are multiplexed with analog functions. every port bit can be independently configured in 4 different modes. 6.4.1 p ort functionality port 0 8-bit bidirectional i/o port with no alternative functions. every port pin can be used as open-drain, standard port, high-impedance input or push-pull output. port 0 is used during emulation mode. port 1 8-bit bidirectional i/o port with alternative functions. every port, except p1.6 and p1.7 can be used as open-drain, standard port, high-impedance input or push-pull output. p1.0 to p1.7 provides the inputs for the external interrupts int2 to int9; the interrupts are enabled by selecting the proper bit in the interrupts enable register p1.1 and p1.2 provide the timer 2 external trigger input (t2ex) and the timer 2 external count input (t2) p1.4 provides the clock output clkout (f psc or f per ) p1.5 provide the timer 2 clock output of the clock-output mode (t2out); to enable output the data sfr must contain logic 1s p1.6 and p1.7 provide the i 2 c-bus clock and data i/o, scl and sda. p1.6 and p1.7 can only be configured as open-drain output or high-impedance input; there is no clamp diode to v dd .i 2 c-bus signals are connected to the port if bit ens1 (s1con sfr) is set to logic 1. port 2 not used. port 3 8-bit bidirectional i/o port with alternative functions. every port can be used as open-drain, standard port, high-impedance input or push-pull output. p3.0 to p3.2 provide the msk output signals mout0, mout1 and mout2 p3.4 also provides the timer 0 external clock input p3.5 also provides the timer 1 external clock input. 6.4.2 p ort i/o configuration each port bit consists of a data latch, two configuration latches, an output driver and an input buffer. the i/o port configurations are determined by the settings in the port configuration sfrs, pncfga and pncfgb, where n indicates the specific port number (0, 1, 3 and 4). the combination of 2 bits in each of the 2 configuration sfrs relates to the output setting for the corresponding port pin, allowing any combination of the 4 i/o modes to be mixed on those port pins. the port i/o configuration types are shown in fig.14 and described in sections 6.4.2.1 to 6.4.2.4. 6.4.2.1 open-drain quasi-bidirectional i/o with n-channel open-drain output. use as an output requires the connection of an external pull-up resistor; all pins have esd protection diodes against v dd and v ss , except for the i 2 c-bus pins p1.6 and p1.7, which have no esd protection to v dd . 6.4.2.2 standard port quasi-bidirectional i/o with pull-up; the strong pull-up p1 is turned on for three clock (f osc ) edges after a low-to-high transition in the port latch; after these three clock edges the port is only weakly driven through p2 and very weakly driven through p3 (see fig.14b). 6.4.2.3 high-impedance input this mode turns off all output drivers on a port. the pin will not source or sink current and may be used as an input-only pin. (see fig.14c). in order not to increase the current consumption the high-impedance input should not float. 6.4.2.4 push-pull output with drive capability in both polarities; under this mode, pins can only be used as outputs (see fig.14d).
2001 jun 19 30 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 table 35 port i/o con?guration types n indicates the speci?c port number (0, 1, 3 and 4). table 36 reset state of port related sfrs note 1. this means all ports, except p0.2, p0.3, p0.4, p1.6 and p1.7 are initialized in standard port configuration driving a weak logic 1. port 0.2 and p0.3 are initialised as open-drain outputs, floating. p0.4 is initialised as bidirectional, driving a strong logic 0. i 2 c-bus i/os p1.6 and p1.7 are initialised in open-drain configuration, floating. the configuration registers (p1cfga.7 to 6 and p1cgb.7 to 6) are however configured as standard port configuration but the connections to the port pmos transistors are not present. type pncfga pncfgb normal ports i 2 c-bus ports open-drain 0 0 open-drain open-drain standard port 1 0 quasi-bidirectional open-drain high-impedance input 0 1 high-impedance input high-impedance input push-pull 1 1 push-pull open-drain sfr description sfr address (hex) state after reset (1) p0 port 0 output data 80 1110 1111 p0cfga port 0 con?guration a 8e 1111 0011 p0cfgb port 0 con?guration b 8f 0000 0000 p1 port 1 output data 90 1111 1111 p1cfga port 1 con?guration a 9e 1111 1111 p1cfgb port 1 con?guration b 9f 0000 0000 p3 port 3 output data b0 1111 1111 p3cfga port 3 con?guration a be 1111 1111 p3cfgb port 3 con?guration b bf 0000 0000
2001 jun 19 31 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 handbook, full pagewidth mbk004 this diode is not implemented on the i 2 c-bus pins v ss v dd external n q from port latch external pull-up i/o pin input data v dd v ss handbook, full pagewidth mbk001 p1 p2 p3 input data 1 oscillator period n v ss v dd strong pull-up i/o pin q from port latch in1 v ss handbook, full pagewidth mbk002 this diode is not implemented on the i 2 c-bus pins input data v dd i/o pin v ss handbook, full pagewidth mbk003 p n strong pull-up q from port latch v ss v dd v dd i/o pin input data v ss fig.14 port configuration options. a. open-drain. b. standard/quasi-bidirectional. c. high-impedance input. d. push-pull.
2001 jun 19 32 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.5 timer 0 and timer 1 event counters timer 0 and timer 1 can perform the following functions: measure time intervals and pulse durations count events measure cpu speed generate interrupt requests. timer 0 and timer 1 can be programmed independently to operate in four modes: mode 0 8-bit timer or 8-bit counter each with divide-by-32 prescaler. mode 1 16-bit time interval or event counter. mode 2 8-bit time interval or event counter with automatic reload upon overflow. mode 3 timer 1 stopped and timer 0 operates as two separate counters. a block diagram of timer 0 and timer 1 with possible clock sources is shown in fig.15. table 37 timer/counter 0 and timer/counter 1 related sfrs sfr description sfr address reset value tcon timer/counter 0 and timer/counter 1 control register 88h 0000 0000 tmod timer/counter 0 and 1 mode control register 89h 0000 0000 syscon system control register b4h 0000 0000 mgt292 c/t = 0 c/t = 1 tl1 th1 th0 c/t = 0 c/t = 1 tl0 t0 tr0 control gate int0 t1 tr1 gate int1 romreq f per f psc instrreq f per f psc control fig.15 timer/counter 0 and 1; clock sources and control logic.
2001 jun 19 33 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.5.1 c lock source signals of t imer 0 and t imer 1 in all four modes timer 0 and timer 1 can be configured to increment from different internal and external clock sources. the tmod and syscon registers must be written to determine the source of the clock signal. after reset the clock source for both timers is connected to the internal clock signal from psc1 (f psc ). the second of four possible clock sources is connected to the other internal clock signal coming from psc2 (f per ). the clock input on both timers has a multiplexer to choose from 4 different clock sources. if the multiplexers are switched to another input by setting user controllable bits in the syscon sfr (bits 7 to 4), the timers can also increment on the other on-chip clock signal coming from psc2 (f per ). in counter mode the timers are incrementing on transitions on the t0 and t1 input pins. first way to enter this mode is by setting control bits c/ t (tmod.6 and 2). second way is to configure syscon to switch the input multiplexer to the clock input signal t1 or t0 while c/ t is logic 0. the latter is also functional even when there is no system clock available. this means when a clock source is supplied on a port pin the timer 1 or 0 can count and generate interrupts even when the chip is in power-down mode. maximum input signal frequency and duty cycle for the timer in counter mode is given in chapter 11. the last multiplexer input to timer 1 and timer 0 is an auxiliary mode which can be used to obtain the operation speed from the handshake cpu. if this mode is activated for the timer 1 input source, the timer increments on every rom request. this means the timer increments by three for a three byte instruction and by two for a two byte instruction etc. if the auxiliary mode is activated for timer 0 the timer increments on every instruction executed by the cpu. this means the timer register holds the number of instructions executed in a certain time frame. this can be used to obtain the number of mips at which the processor is running. the syscon register is described in section 6.5.5. 6.5.2 o perating modes of t imer 0 and t imer 1 the timer or counter function is selected by control bits c/ t in the special function register tmod. these two timer/counters have four operating modes, which are selected by bit-pairs (m1 and m0) in tmod. modes 0, 1, and 2 are the same for both timers/counters. mode 3 configures timer 0 while timer 1 is disabled. the four operating modes are: mode 0 putting either timer 0 or timer 1 into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. figure 16 shows the mode 0 operation as it applies to timer 1. in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all logic 1s to all logic 0s, it sets the timer interrupt flag tf1. timer 1 is enabled when tr1 = 1. with gate = 0, it is continuously counting, setting gate = 1, the timer is controlled by the external input int1, to facilitate pulse width measurements. tr1 is a control bit in the sfr tcon (see section 6.5.3). gate is in tmod. the 13-bit register consists of all 8 bits of th1 and the lower 5 bits of tl1. the upper 3 bits of tl1 are indeterminate and should be ignored. setting the run flag (tr1) does not clear the registers. mode 0 operation is the same for timer 0 as for timer 1. substitute tr0, tf0, and int0 for the corresponding timer 1 signals in fig.16. there are two different gate bits, one for timer 1 (tmod.7) and one for timer 0 (tmod.3). mode 1 is the same as mode 0, except that the timer register is being run with all 16 bits. mode 2 configures the timer register as an 8-bit counter (tl1) with automatic reload, as shown in fig.17. overflow from tl1 not only sets tf1, but also reloads tl1 with the contents of th1, which is preset by software. the reload leaves th1 unchanged. mode 2 operation is the same for timer/counter 0. mode 3 timer 1 in mode 3 simply holds its count. the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as two separate counters. the logic for mode 3 on timer 0 is shown in fig.18. tl0 uses the timer 0 control bits: c/ t, gate, tr0, int0, and tf0. th0 is locked into a timer function and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the timer 1 interrupt. mode 3 is provided for applications requiring an extra 8-bit timer on the counter. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3 or in any application not requiring an interrupt.
2001 jun 19 34 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 mgt293 tl1 (5 bits) t1 tr1 gate int1 control romreq f per f psc c/t = 0 th1 (8 bits) tf1 interrupt c/t = 1 fig.16 timer/counter 0 and 1; mode 0: 13-bit counter. mgt294 tl1 (8 bits) t1 tr1 gate int1 tf1 control reload interrupt romreq f per f psc c/t = 0 th1 (8 bits) c/t = 1 fig.17 timer/counter 0 and 1; mode 2: 8-bit auto-reload. mgt295 tl0 (8 bits) t0 tr0 gate tr1 1 / 12 f osc int0 tf0 control interrupt romreq f per f psc c/t = 0 th0 (8 bits) tf1 control interrupt c/t = 1 fig.18 timer/counter 0 and 1; mode 3: two 8-bit counters.
2001 jun 19 35 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.5.3 t imer /c ounter 0 and 1c ontrol r egister (tcon) table 38 timer/counter 0 and 1 control register (sfr address 88h) table 39 description of tcon bits note 1. if the timer 0 or timer 1 is not enabled (tr0 or tr1), the clock to timer 0/1 is switched off for power saving. 6.5.4 t imer /c ounter 0 and 1m ode c ontrol r egister (tmod) table 40 timer/counter 0 and 1 mode control register (sfr address 89h) table 41 description of tmod bits 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit symbol description 7 tf1 timer 1 over?ow ?ag. set by hardware on timer/counter overflow; cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. 6 tr1 timer 1 run control bit. set/cleared by software to turn timer/counter on/off; note 1. 5 tf0 timer 0 over?ow ?ag. set by hardware on timer/counter overflow; cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. 4 tr0 timer 0 run control bit. set/cleared by software to turn timer/counter on/off; note 1. 3 ie1 interrupt 1 edge ?ag. set by hardware when external interrupt edge detected; cleared when interrupt processed. 2 it1 interrupt 1 type control bit. set/cleared by software. if it1 = 1, then external interrupt is low-level triggered. if it1 = 0, then external interrupt is falling edge triggered. 1 ie0 interrupt 0 edge ?ag. set by hardware when external interrupt edge detected; cleared when interrupt processed. 0 it0 interrupt 0 type control bit. set/cleared by software. if it0 = 1, then external interrupt is low-level triggered. if it0 = 0, then external interrupt is falling edge triggered. 76543210 gate c/ tm1 m0gatec/ tm1 m0 bit symbol description 7gate gating control. when set timer/counter 1 is enabled only while int1 pin is high and tr1 control pin is set; when cleared timer 1 is enabled whenever tr1 control bit is set. 6c/ t timer or counter selector. cleared for timer operation (counts on f psc ); set for counter operation (input from t1 input pin). 5m1 timer 1 mode select. see table 42. 4m0 3gate gating control. when set timer/counter 0 is enabled only while int0 pin is high and tr0 control pin is set; when cleared timer 0 is enabled whenever tr0 control bit is set. 2c/ t timer or counter selector. cleared for timer operation (counts on f psc ); set for counter operation (input from t0 input pin). 1m1 timer 0 mode select. see table 42. 0m0
2001 jun 19 36 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 table 42 timer 0 and timer 1 mode select n=0or1. 6.5.5 s ystem c ontrol r egister (syscon) table 43 system control register (sfr address b4h; reset value = 0000 0000) table 44 description of syscon bits table 45 timer 1 input source select modes table 46 timer 0 input source select modes m1 m0 description 00 8048-type timer. tln serves as 5-bit prescaler 01 16-bit timer/counter. thn and tln are cascaded; there is no prescaler 10 8-bit auto-reload timer/counter. thn holds a value which is to be reloaded into tln each time it over?ows. 11 timer 0. tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits; th0 is an 8-bit timer only controlled by timer 1 control bits. timer 1. timer/counter 1 stopped. 76543210 t1src1 t1src0 t0src1 t0src0 -- select xtm bit symbol description 7 t1src1 timer 1 clock source select bit 1 and 0; see table 45 6 t1src0 5 t0src1 timer 0 clock source select bit 1 and 0; see table 46 4 t0src0 3 - do not use 2 - 1 select comparator select bit; see section 6.1 0 xtm oscillator disable bit; see section 6.1 t1src1 t1src0 description 00f psc is the timer 1 clock input 0 1 t1 is the timer 1 clock input 1 0 the romreq signal is the timer 1 clock input 11f per is the timer 1 clock input t0src1 t0src0 description 00f psc is the timer 0 clock input 0 1 t0 is the timer 0 clock input 1 0 the instruction request signal is the timer 0 clock input 11f per is the timer 0 clock input
2001 jun 19 37 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.6 timer 2 timer 2 is a 16-bit timer/counter which can operate as either an event timer or an event counter. timer 2 has three operating modes: capture, auto-reload up/down counting and clock output mode. the modes are selected using t2con. 6.6.1 t imer 2s pecial f unction r egisters timer 2 has six sfrs that can be read and written by the cpu. these registers are: t2con, t2mod, t2h, t2l, t2rch and t2rcl. timer 2 register values can be changed by hardware or software. if an update by hardware and software occurs in one of the registers t2h, t2l, t2rch or t2rcl, the update by software has precedence. table 47 timer 2 related sfrs 6.6.1.1 timer 2 control register (t2con) table 48 timer 2 control register (sfr address c8h) table 49 description of t2con bits sfr description sfr address reset value t2con timer 2 control register c8h 00xx 0000 t2mod timer 2 mode register c9h xxxx x000 t2l timer 2 low byte count register cch 0000 0000 t2h timer 2 high byte count register cdh 0000 0000 t2rcl timer 2 low byte capture/reload register cah 0000 0000 t2rch timer 2 high byte capture/reload register cbh 0000 0000 76543210 t2f exf2 -- exen2 tr2 c/ t2 cp/ rl2 bit symbol description 7 t2f timer 2 over?ow ?ag. set by a timer 2 overflow and must be cleared by software. tf2 will not be set when clock out mode is selected. 6 exf2 timer 2 external ?ag. set on a negative transition on t2ex and bit exen2 = 1. in auto-reload mode it is toggled on an under- or over?ow; this bit must be cleared by software. 5 and 4 - these 2 bits are reserved each must be set to logic 0. 3 exen2 timer 2 external enable ?ag. set by software only; when set, allows a capture or reload to occur, together with an interrupt, as a result of a negative transition on input t2ex if in capture mode or auto-reload mode with dcen reset. if in auto-reload mode and dcen is set, the exen2 bit has no in?uence. in the other modes exf2 is set and an interrupt is generated on a high-to-low transition on the t2ex pin. when exen2 is reset, timer 2 ignores events on pin t2ex in all modes. 2 tr2 start/stop control for timer 2. set by software only; when set, the timer is started; when reset the timer is stopped. if timer 2 is not enabled (tr2 = 0), the clock to timer 2 is switched off for power saving. 1c/ t2 timer/counter select for timer 2. set by software only; when set the counter function is selected, when reset the timer function is selected. 0 cp/ rl2 capture/reload ?ag. set by software only; selection of mode capture or reload; when set the capture function is selected, when reset the reload function is selected.
2001 jun 19 38 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.6.1.2 timer 2 mode register (t2mod) table 50 timer 2 mode register (sfr address c9h) table 51 description of t2mod bits 6.6.1.3 t2h and t2l registers these registers are normal registers in the sfr space. they are the actual timer/counter registers. on the fly reading can give a wrong value since t2h can be changed after t2l is read and before t2h is read. this situation is indicated by flag t2rd in t2mod sfr. in all cases the two 8-bit registers operate as one 16-bit timer/counter register. 6.6.1.4 t2rch and t2rcl registers these registers are normal registers in the sfr space. they are the capture and reload registers depending on the chosen operation mode. in the capture mode the t2rch/t2rcl registers are loaded with the value of the t2h/t2l registers. in the reload mode the t2h/t2l registers are loaded with the value of the t2rch/t2rcl registers. 76543210 ----- t2rd c/t2oe cp/dcen bit symbol description 7to3 - reserved; must be kept to logic 0. 2 t2rd timer 2 read ?ag. set/reset by hardware only. this bit is set by hardware if a t2l read operation is followed by an increment of t2h before a t2h read operation. this bit is reset on the trailing edge of the next t2l read. this bit is used to indicate that the 16-bit timer 2 register is not read properly since the t2h part was incremented by hardware before it was read. 1 c/t2oe timer 2 output enable bit. set by software only. when set and t2con.tf2 is reset and t2con.exf2 is reset, output t2 outputs a clock signal. when this condition is not met, output t2 outputs a logic 1. the clock output is half the over?ow frequency of timer 2. 0 cp/dcen down count enable ?ag. set by software only. when this bit is set and input t2ex is set timer 2 can be con?gured (in auto-reload mode) as an up counter. when this bit is reset or input t2ex is reset, timer 2 can be con?gured (in auto-reload mode) as a down counter.
2001 jun 19 39 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.6.2 t imer 2 modes in general timer 2 can operate in three different modes: capture mode auto-reload mode clock output mode. in these three modes the timer/counter operates on events detected on inputs t2 and t2ex. table 52 shows the list of t2con and t2mod register bits which set the timer 2 mode of operation. sections 6.6.3 to 6.6.5 describe the timer 2 modes. table 52 timer 2 modes 6.6.3 c apture mode in the capture mode, registers t2rch/t2rcl are used to capture the t2h/t2l register data. there are two options selected by the t2con.exen2 bit. this bit enables or disables the events of the external trigger input t2ex. t2con.c/ t2 = 1: timer 2 is a 16-bit counter. the counter increments at each low-to-high transition on input t2 at a maximum rate of one each 12 f psc cycles. t2con.c/ t2 = 0: timer 2 is a 16-bit timer. the timer increments each 6 f psc cycles. t2con.exen2 = 1: the external trigger input t2ex is enabled. timer 2 is a 16-bit timer or counter. C if t2mod.dcen = 0, a high-to-low transition at input t2ex causes the current timer 2 value (t2h/t2l data) to be captured into t2rch/t2rcl, and bit t2con.exf2 becomes set. C if t2mod.dcen = 1, bit t2con.exen2 has no influence. overflowing of timer 2 sets bit t2con.tf2. t2con.exen2 = 0: the external trigger input t2ex is disabled. timer 2 is a 16-bit timer or counter. the t2ex input is ignored. overflowing of timer 2 sets bit t2con.tf2. the capture mode is shown in fig.19. cp/ rl2 c/t2oe c/ t2 operating mode 0 0 x 16-bit auto-reload 1 0 x 16-bit capture 0 1 0 clock output handbook, full pagewidth mbh998 tl2 (8 bits) comparator 1 (16 bits) tr2 control th2 (8 bits) comp2l comp2h ecomp rcap2l rcap2h exf2 tf2 comp timer 2 interrupt port p1.2 exen2 control c/t2 = 1 t2 pin 6 osc transition detector t2ex pin c/t2 = 0 capture fig.19 timer 2 in capture mode.
2001 jun 19 40 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.6.4 a uto - reload mode in the auto-reload mode, timer 2 can be configured as a timer or a counter (t2con.c/ t2 bit) and then programmed to count up or down. the counting direction is determined by bit t2mod.dcen (down count enable). when reset is applied, then t2mod.dcen is reset which defaults to counting up. if t2mod.dcen is set, timer 2 can count up when t2ex = 1 and count down when t2ex = 0. t2con.c/ t2 = 1: timer 2 is a 16-bit counter. the counter increments/decrements at each low-to-high transition on input t2 at a maximum rate of one each 12 f psc cycles. t2con.c/ t2 = 0: timer 2 is a 16-bit timer. the timer increments/decrements each 6 f psc cycles. 6.6.4.1 t2mod.dcen = 0: counting up in the auto-reload mode and counting up, registers t2rch/t2rcl are used to hold a reload value for t2h/t2l. by setting bit t2con.exen2 the external trigger input t2ex is enabled. when resetting bit t2con.exen2, the external trigger input t2ex is disabled. t2con.exen2 = 1: the external trigger input t2ex is enabled. timer 2 is a 16-bit timer or counter. a high-to-low transition at input t2ex causes the value in t2rch/t2rcl to be reloaded in the timer 2 t2h/t2l registers, and bit t2con.exf2 becomes set. also overflowing of timer 2 causes the value in t2rch/t2rcl to be reloaded in the t2h/t2l registers and sets bit t2con.tf2. t2con.exen2 = 0: the external trigger input t2ex is disabled. timer 2 is a 16-bit timer or counter. the t2ex input is ignored. overflowing of timer 2 causes the value in t2rch/t2rcl to be reloaded in the t2h/t2l registers and sets bit t2con.tf2. timer 2 interrupt will be set if exf2 is set or tf2 is set. the auto-reload mode (dcen = 0) is shown in fig.20. handbook, full pagewidth mbh999 tl2 (8 bits) comparator 1 (16 bits) tr2 control th2 (8 bits) comp2l comp2h ecomp rcap2l rcap2h exf2 tf2 comp timer 2 interrupt port p1.2 exen2 control c/t2 = 1 t2 pin 6 osc transition detector t2ex pin c/t2 = 0 reload fig.20 timer 2 in auto-reload mode (dcen = 0).
2001 jun 19 41 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.6.4.2 t2mod.dcen = 1: t2ex = 1: counting up the high value of the external trigger input t2ex sets timer 2 to a count-up mode. in the auto-reload mode and counting up, registers t2rch/t2rcl are used to hold a reload value for t2h/t2l. overflowing of timer 2 causes the value in t2rch/t2rcl to be reloaded in the t2h/t2l registers, sets bit t2con.tf2 and toggles bit t2con.exf2 (t2con.exf2 can be used as 17th bit if desired). timer 2 interrupt will be set if tf2 is set. 6.6.4.3 t2mod.dcen = 1: t2ex = 0: counting down the low value of the external trigger input t2ex sets timer 2 to a count down mode. in the auto-reload mode and counting down, registers t2rch/t2rcl are used to hold a value for detecting an underflow of t2h/t2l. underflow occurs if the contents of t2h/t2l matches the contents of t2rch/t2rcl. upon underflow, bit tf2 will be set and registers t2h/t2l will be loaded with ffffh, bit t2con.tf2 is set and bit t2con.exf2 toggles (t2con.exf2 can be used as 17th bit if desired). note that a timer 2 roll over from 0000h to ffffh is not considered as an underflow (only when t2rch/t2rcl = 0000h). timer 2 interrupt will be set if tf2 is set. the auto-reload mode (dcen = 1) is shown in fig.21. mgt296 t2l tr2 control t2h tf2 down count reload value upcount reload value t2rcl t2rch ffh ffh exf2 toggle t2ex: 1 = count up 0 = count down timer 2 interrupt c/ t2 = 1 t2 f psc c/ t2 = 0 fig.21 timer 2 in auto-reload mode (dcen = 1).
2001 jun 19 42 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.6.5 c lock output mode in the clock output mode, the output t2out is enabled as a clock output. a timer overflow will cause t2h/t2l to be loaded with t2rch/t2rcl and will toggle output t2out. the frequency of pin t2out is half the overflow frequency. bit t2con.exf2 will be set if t2con.exen2 is set and a high-to-low transition is detected on the t2ex pin. timer 2 interrupt will be set only if t2con.exf2 is set. this makes an extra external interrupt available. if timer 2 does not operate in the clock output mode, the output t2out remains as specified by the i/o sfrs. the clock output mode is shown in fig.22. mgt297 t2l tr2 t2h t2rcl t2rch exf2 t2ex toggle timer 2 interrupt t2out f psc exen2 t2oe c/ t2 fig.22 timer 2 in clock output mode.
2001 jun 19 43 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.7 watchdog timer the watchdog timer consists of an 8-bit down counter and a watchdog prescaler. the binary number defined by bits wd3 to wd0 (wdcon sfr), the watchdog prescaler and the timer prescaler (f psc ) defines the expiration time of the watchdog timer. once enabled this counter runs continuously. once expired the timer produces firstly an interrupt and finally a reset. the software must reload the watchdog timer at regular intervals to avoid expiration. a positive edge on bit ld (wdcon sfr) (re)loads the counter with the value of wd3 to wd0, sets the low bits to logic 1 and activates this counter if it is not yet running. however, to prepare the (re)loading a positive edge must be applied to the cond bit in wdcon. in this way at least two locations in software are needed before the counter can be reloaded. after reset the counter is not running. only after the first load (ld) it is clocked continuously by a clock pulse. if the next ld signal is not given within the defined expiration interval an overflow occurs and the processor will be reset (signal wdr). one clock cycle (seen from the watchdog prescaler output) before the reset is applied a wdi interrupt is issued. this gives the opportunity to avoid the reset if required. the maximum watchdog timer expiration time is thus 254/f psc to the wd interrupt and 255/f psc to the reset. 6.7.1 w atchdog t imer c ontrol r egister (wdcon) the wdcon sfr is used to control the operation of the on-chip watchdog timer. if the watchdog timer is not loaded after reset, the clock to the watchdog timer is switched off for power saving. table 53 watchdog timer control register (sfr address a5h; reset value = 0000 0000) table 54 description of wdcon bits 76543210 cond wd3 wd2 wd1 wd0 mskpol - ld bit symbol description 7 cond load condition; control signal from processor 6 wd3 wd0 to wd3 is the preset value for the high nibble of the watchdog timer 5 wd2 4 wd1 3 wd0 2 mskpol this bit controls the polarity of the input signal to the msk modem; mskpol = 0: input directly connected to the msk modem mskpol = 1: input inverted and connected to the msk modem 1 - reserved, must be kept to logic 0 0 ld load watchdog timer with wd0 to wd3; control signal from cpu
2001 jun 19 44 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.7.2 w atchdog t imer p rescaler r egister (wdtim) the wdtim sfr is used to initialize the prescaler of the on-chip watchdog timer. table 55 watchdog timer prescaler register (sfr address a6h; reset value 0000 0000) the expiration time (t exp) can be calculated as follows: where: prescaler factor = the dividing factor from prescaler (psc1 and psc2); 1, 2, 4, 6, 8, 10, 12 and 16 wdtim = the 8-bit value (0 to 255) in the watchdog timer prescaler register wdcon = the 4-bit value (0 to 15) reloaded in the watchdog timer clock period = the period of the signal applied to pin xtal1. from the t exp formulae it follows that the maximum expiration time is: t exp(max) =16 (2 + 64 256) 16 (16) (clock period) = 67 206 016 (clock period) and the minimum expiration time is: t exp(min) =1 66 16 (clock period) = 1056 (clock period) 6.7.3 e xample sequence to reload the w atchdog t imer an example of the reload sequence for the watchdog timer: mov wdcon,#00h;clear cond and ld bit orl wdcon,#80h;positive edge wdcon.7, prepare condition orl wdcon,#01h;positive edge wdcon.0, reload the timer 76543210 wdtim.7 wdtim.6 wdtim.5 wdtim.4 wdtim.3 wdtim.2 wdtim.1 wdtim.0 mgt298 watchdog timer watchdog prescaler (wdtim) f psc fig.23 clocking the watchdog timer. t exp prescaler factor () 2 64 wdtim 1 + () + {} 16 wdcon 1 + () clock period () =
2001 jun 19 45 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.8 i 2 c-bus serial i/o (master/slave interface) the i 2 c-bus implements a master/slave i 2 c-bus interface with integrated shift register, shift timing generation and slave address recognition. i 2 c-bus standard mode (100 khz sclk) and fast mode (400 khz sclk) are supported. low speed mode and extended 10-bit addressing are not supported. the i 2 c-bus consists of two lines: a data line (sda) and a clock line (scl). these lines also function as the i/o port lines p1.7 and p1.6 respectively. the system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. the i 2 c-bus serial i/o has complete autonomy in byte handling and operates in 4 modes: master transmitter master receiver slave transmitter slave receiver. these functions are controlled by the s1con register. s1sta is the serial status register whose contents may also be used as a vector to various service routines. s1dat is the data shift register and s1adr the slave address register. slave address recognition is performed by on-chip hardware. the block diagram of the i 2 c-bus serial i/o is shown in fig.24. the interface between the cpu and the i 2 c-bus logic, referred to as sio1, is accomplished with four special function registers (see table 56): the i 2 c-bus interface is compliant to the specification as described in the i 2 c-bus and how to use it (ordering number 9398 393 40011). this document includes also a detailed description of the i 2 c-bus protocol. table 56 i 2 c-bus related sfrs sfr description sfr address reset value s1con serial control register d8h 0000 0000 s1dat data shift register dah 0000 0000 s1adr address register dbh 0000 0000 s1sta serial status register d9h 1111 1000
2001 jun 19 46 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.8.1 s erial c ontrol r egister (s1con) the cpu can read from and write to this 8-bit sfr. two bits are affected by the sio1 hardware: the si bit is set when a serial interrupt is requested, and the sto bit is cleared when a stop condition is present on the i 2 c-bus. the sto bit is also cleared when ens1 = 0. reset initializes s1con to 00h. table 57 serial control register (sfr address d8h) table 58 description of s1con bits 76543210 cr2 ens1 sta sto si aa cr1 cr0 bit symbol description 7 cr2 this bit along with bits cr1 and cr0 determines the serial clock frequency when sio is in the master mode; see table 59. when cr2 = 0 the i 2 c-bus is in fast mode. 6 ens1 enable serial i/o. when ens1 = 0, the serial i/o is disabled. sda and scl outputs are in the high-impedance state; p1.6 and p1.7 function as open-drain ports. when ens1 = 1, the serial i/o is enabled. output port latches p1.6 and p1.7 must be set to logic 1; note 1. 5sta start ?ag. when this bit is set in slave mode, the sio hardware checks the status of the i 2 c-bus and generates a start condition if the bus is free or after the bus becomes free. if sta is set while the sio is in master mode, sio will generate a repeated start condition. ens1 should not be used to temporarily release sio1 from the i 2 c-bus since, when ens1 is reset, the i 2 c-bus status is lost. the aa flag should be used instead. 4sto stop ?ag. when the sto bit is set while sio1 is in a master mode, a stop condition is transmitted to the i 2 c-bus. when the stop condition is detected on the bus, the sio1 hardware clears the sto ?ag. in a slave mode, the sto ?ag may be set to recover from an error condition. in this case, no stop condition is transmitted to the i 2 c-bus. however, the sio1 hardware behaves as if a stop condition has been received and switches to the de?ned not addressed slave receiver mode. the sto ?ag is automatically cleared by the hardware. if the sta and sto bits are both set, the stop condition is transmitted to the i 2 c-bus if sio1 is in a master mode (in a slave mode, sio1 generates an internal stop condition which is not transmitted). sio1 then transmits a start condition. when the sto bit is reset, no stop condition will be generated. 3si sio interrupt ?ag. this flag is set, and an interrupt is generated, after any of the following events occur: a start condition is generated in master mode own slave address has been received during aa = 1 the general call address has been received while s1adr0 = 1 and aa = 1 a data byte has been received or transmitted in master mode (even if arbitration is lost) a data byte has been received or transmitted as selected slave a stop or start condition is received as selected slave receiver or transmitter. if this ?ag is set, the i 2 c-bus is halted (by pulling down scl). received data is only valid until this ?ag is reset.
2001 jun 19 47 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 note 1. if the serial i/o is not enabled (ens1), the clock to the serial i/o is switched off for power saving. table 59 selection of the serial clock frequency in the master mode of operation bit rates greater than 400 khz are outside the speci?ed frequency range. 2aa assert acknowledge. when this bit is set, an acknowledge (low level to sda) is returned during the acknowledge clock pulse on the scl line when: own slave address is received general call address is received (s1adr.0 = 1) a data byte is received while the device is programmed to be a master receiver a data byte is received while the device is a selected slave receiver. when sio1 is in the addressed slave transmitter mode, state c8h will be entered after the last serial bit is transmitted. when si is cleared, sio1 leaves state c8h, enters the not addressed slave receiver mode, and the sda line remains at a high level. in state c8h, the aa ?ag can be set again for future address recognition. when sio1 is in the not addressed slave mode, its own slave address and the general call address are ignored. consequently, no acknowledge is returned, and a serial interrupt is not requested. thus, sio1 can be temporarily released from the i 2 c-bus while the bus status is monitored. while sio1 is released from the bus, start and stop conditions are detected, and serial data is shifted in. address recognition can be resumed at any time by setting the aa ?ag. if the aa ?ag is set when the parts own slave address or the general call address has been partly received, the address will be recognized at the end of the byte transmission. when this bit is reset, no acknowledge is returned. consequently, no interrupt is requested when the own slave address or general call address is received. 1 cr1 these two bits along with the cr2 bit determine the serial clock frequency when sio is in the master mode; see table 59. 0 cr0 cr2 cr1 cr0 f per divisor bit rate (khz) at f per 3.58 mhz 4 mhz 6 mhz 0 0 0 10 358 400 (600) 0 0 1 20 179 200 300 0 1 0 30 119.33 133 199.5 0 1 1 40 89.5 100 150 1 0 0 80 44.75 50 75 1 0 1 120 29.83 33 49.5 1 1 0 160 22.38 25 37.5 1 1 1 not valid selection --- bit symbol description
2001 jun 19 48 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.8.2 d ata s hift r egister (s1dat) s1dat contains a byte of serial data to be transmitted or a byte which has just been received. the cpu can read from and write to this 8-bit sfr while it is not in the process of shifting a byte. this occurs when sio1 is in a defined state and the serial interrupt flag is set. data in s1dat remains stable as long as si is set. data in s1dat is always shifted from right to left: the first bit to be transmitted is the msb (bit 7) and after a byte has been received, the first bit of received data is located at the msb of s1dat. while data is being shifted out, data on the bus is simultaneously being shifted in; s1dat always contains the last data byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in s1dat. reset initializes s1dat to 00h. s1dat and the ack flag form a 9-bit shift register which shifts in or shifts out an 8-bit byte, followed by an acknowledge bit. the ack flag is controlled by the sio1 hardware and cannot be accessed by the cpu. serial data is shifted through the ack flag into s1dat on the rising edges of clock pulses on the scl line. when a byte has been shifted into s1dat, the serial data is available in s1dat, and the acknowledge bit is returned by the control logic during the ninth clock pulse. serial data is shifted out from s1dat via a buffer on the falling edges of clock pulses on the scl line. when the cpu writes to s1dat, the buffer is loaded with the contents of s1dat.7 which is the first bit to be transmitted to the sda line. after nine serial clock pulses, the eight bits in s1dat will have been transmitted to the sda line, and the acknowledge bit will be present in ack. note that the eight transmitted bits are shifted back into s1dat. table 60 data shift register (sfr address dah) table 61 description of s1dat bits 76543210 s1dat.7 s1dat.6 s1dat.5 s1dat.4 s1dat.3 s1dat.2 s1dat.1 s1dat.0 bit symbol description 7 to 1 s1dat.[7:0] eight data bits, to be transmitted or just received. a logic 1 in s1dat corresponds to a high level on the i 2 c-bus, and a logic 0 corresponds to a low level on the bus. serial data transmission of s1dat is msb ?rst.
2001 jun 19 49 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.8.3 a ddress r egister (s1adr) the cpu can read from and write to this 8-bit sfr. s1adr is not affected by the sio1 hardware. the contents of this register are irrelevant when sio1 is in a master mode. in the slave modes, the seven most significant bits must be loaded with the microcontrollers own slave address, and, if the least significant bit is set, the general call address (00h) is recognized; otherwise it is ignored. reset initializes s1adr to 00h. table 62 address register (sfr address dbh) table 63 description of s1adr bits 6.8.4 s erial s tatus r egister (s1sta) s1sta is an 8-bit read-only special function register. the three least significant bits are always zero. the five most significant bits contain the status code. there are 26 possible status codes. when s1sta contains f8h, no relevant state information is available and no serial interrupt is requested. reset initializes s1sta to f8h. all other s1sta values correspond to defined sio1 states. when each of these states is entered, a serial interrupt is requested (si = 1). the status codes for all possible modes of the i 2 c-bus interface are given in table 66. the contents of this register may be used as a vector to a service routine. this optimizes the response time of the software and consequently that of the i 2 c-bus. s1sta is a read-only register. table 64 serial status register (sfr address d9h) table 65 description of s1sta bits 76543210 sla6 sla5 sla4 sla3 sla2 sla1 sla0 gc bit symbol description 7 to 1 sla[6:0] these bits correspond to the 7-bit slave address which will be recognized on the incoming data stream from the i 2 c-bus; when the slave address is detected and the interface is enabled, a serial interrupt will be generated to the cpu. 0 gc this bit is used to determine whether the general call address is recognized. when a logic 0, the general call address is not recognized; when a logic 1, the general call address is recognized. 76543210 sc4 sc3 sc2 sc1 sc0 0 0 0 bit symbol description 3 to 7 sc[4:0] 5-bit status code 0to2 - these three bits are held low
2001 jun 19 50 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 table 66 status codes for the different modes s1sta value description mst/trx mode 08h a start condition has been transmitted 10h a repeated start condition has been transmitted 18h sla and w have been transmitted, ack has been received 20h sla and w have been transmitted, a ck received 28h data of s1dat has been transmitted, ack received 30h data of s1dat has been transmitted, a ck received 38h arbitration lost in sla, r/w or data mst/rec mode 38h arbitration lost while returning a ck 40h sla and r have been transmitted, ack received 48h sla and r have been transmitted, a ck received 50h data has been received, ack returned 58h data has been received, a ck returned slv/rec mode 60h own sla and w have been received, ack returned 68h arbitration lost in sla, r/w as mst; own sla and w have been received, ack returned 70h general call has been received, ack returned 78h arbitration lost in sla, r/w as mst; general call has been received 80h previously addressed with own sla; data byte received, ack returned 88h previously addressed with own sla; data byte received, a ck returned 90h previously addressed with general call; data byte has been received, ack has been returned 98h previously addressed with general call; data byte has been received, a ck has been returned a0h a stop condition or repeated start condition has been received while still addressed as slv/rec or slv/trx slv/trx mode a8h own sla and r have been received, ack returned b0h arbitration lost in sla, r/w as mst. own sla and r have been received, ack returned b8h data byte has been transmitted, ack received c0h data byte has been transmitted, a ck received c8h last data byte has been transmitted (aa = 0), ack received miscellaneous 00h bus error during mst mode or selected slv mode, due to an erroneous start or stop condition f8h no information available (reset value). the serial interrupt ?ag si, is not yet set
2001 jun 19 51 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 table 67 symbols used in table 66 symbol description sla 7-bit slave address r read bit w write bit ack acknowledgement (acknowledge bit = logic 0) a ck no acknowledgement (acknowledge bit = logic 1) data 8-bit data byte to or from i 2 c-bus mst master slv slave trx transmitter rec receiver 6.8.5 m odes of operation the i 2 c-bus logic may operate in any of the following four modes: master transmitter master receiver slave transmitter slave receiver. as a master, the i 2 c-bus logic will generate all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the i 2 c-bus will not be released. two types of data transfers are possible on the i 2 c-bus: data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows the data bytes transmitted by the slave to the master. the master returns an acknowledge bit after each received byte except the last byte. at the end of the last received byte, a not acknowledge is returned. in a given application, sio1 may operate as a master and as a slave. in the slave mode, the sio1 hardware looks for its own slave address and the general call address. if one of these addresses is detected, an interrupt is requested. when the microcontroller wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. if bus arbitration is lost in the master mode, sio1 switches to the slave mode immediately and can detect its own slave address in the same serial transfer. 6.8.5.1 master transmitter mode serial data is output through sda while scl outputs the serial clock. the first byte transmitted contains the slave address (7-bit sla) of the receiving device and the data direction bit. in this case the data direction bit (r/w) will be a logic 0 (w). serial data is transmitted 8 bits at a time. after each byte is transmitted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in the master transmitter mode, a number of data bytes can be transmitted to the slave receiver. before the master transmitter mode can be entered, s1con must be initialized with the ens1 bit set and the sta, sto and si bits reset. ens1 must be set to enable the sio1 interface. if the aa bit is reset, sio1 will not acknowledge its own slave address or the general call address if they are present on the bus. this will prevent the sio1 interface from entering a slave mode.
2001 jun 19 52 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 the master transmitter mode may now be entered by setting the sta bit. the sio1 logic will then test the i 2 c-bus and generate a start condition as soon as the bus becomes free. when a start condition is transmitted, the serial interrupt flag (si) is set, and the status code in the status register (s1sta) will be 08h. this status code must be used to vector to an interrupt service routine that loads s1dat with the slave address and the data direction bit (sla + w). the si bit in s1con must then be reset before the serial transfer can continue. when the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in s1sta are possible. the appropriate action to be taken for any of the status codes is detailed in the table. after a repeated start condition (state 10h), sio1 may switch to the master receiver mode by loading s1dat with sla + r. 6.8.5.2 master receiver mode the first byte transmitted contains the slave address of the transmitting device (7-bit sla) and the data direction bit. in this case the data direction bit (r/w) will be logic 1 (r). serial data is received via sda while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are output to indicate the beginning and end of a serial transfer. in the master receiver mode, a number of data bytes are received from a slave transmitter. the transfer is initialized as in the master transmitter mode. when the start condition has been transmitted, the interrupt service routine must load s1dat with the 7-bit slave address and the data direction bit (sla + r). the si bit in s1con must then be cleared before the serial transfer can continue. when the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes are possible in s1sta. the appropriate action to be taken for each of the status codes is detailed in the table. after a repeated start condition (state 10h), sio1 may switch to the master transmitter mode by loading s1dat with sla + w. 6.8.5.3 slave receiver mode serial data and the serial clock are received through sda and scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. in the slave receiver mode, a number of data bytes are received from a master transmitter. to initiate the slave receiver mode, s1adr must be loaded with the 7-bit slave address to which sio1 will respond when addressed by a master. also the least significant bit of s1adr should be set if the interface should respond to the general call address (00h).the serial control register (s1con) should be initialized with ens1 and aa set and sta, sto, and si reset in order to enter the slave receiver mode. setting the aa bit will enable the logic to acknowledge its own slave address or the general call address and ens1 will enable the interface. when s1adr and s1con have been initialized, sio1 waits until it is addressed by its own slave address followed by the data direction bit which must be logic 0 (w) for sio1 to operate in the slave receiver mode. after its own slave address and the w bit have been received, the serial interrupt flag (si) is set and a valid status code can be read from s1dat. this status code should be used to vector to an interrupt service routine, and the appropriate action to be taken for each of the status codes is detailed in table 66. the slave receiver mode may also be entered if arbitration is lost while sio1 is in the master mode. if the aa bit is reset during a transfer, sio1 will return a not acknowledge (logic 1) to sda after the next received data byte. while aa is reset, sio1 does not respond to its own slave address or a general call address. however, the i 2 c-bus is still monitored and address recognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate sio1 from the i 2 c-bus. 6.8.5.4 slave transmitter mode the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit will indicate that the transfer direction is reversed. serial data is transmitted via sda while the serial clock is input through scl. start and stop conditions are recognized as the beginning and end of a serial transfer. in the slave transmitter mode, a number of data bytes are transmitted to a master receiver. data transfer is initialized as in the slave receiver mode. when s1adr and s1con have been initialized, sio1 waits until it is addressed by its own slave address followed by the data direction bit which must be logic 1 (r) for sio1 to operate in the slave transmitter mode.
2001 jun 19 53 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 after its own slave address and the r bit have been received, the serial interrupt flag (si) is set and a valid status code can be read from s1sta. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in the table. the slave transmitter mode may also be entered if arbitration is lost while sio1 is in the master mode. if the aa bit is reset during a transfer, sio1 will transmit the last byte of the transfer and enter state c0h or c8h. sio1 is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. thus the master receiver receives all logic 1s as serial data. while aa is reset, sio1 does not respond to its own slave address or a general call address. however, the i 2 c-bus is still monitored, and address recognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate sio1 from the i 2 c-bus. 6.8.6 f unctional description i 2 c- bus interface 6.8.6.1 input ?lter input signals sda and scl from i/o pad cells are synchronized with f per , and spikes shorter than three clock periods are filtered out. 6.8.6.2 arbitration and control logic in the master transmitter mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the i 2 c-bus. if another device on the bus overrules a logic 1 and pulls the sda line low, arbitration is lost, and sio1 immediately changes from master transmitter to slave receiver. sio1 will continue to output clock pulses (on scl) until transmission of the current serial byte is complete. arbitration may also be lost in the master receiver mode. loss of arbitration in this mode can only occur while sio1 is returning a not acknowledge (logic 1) to the bus. arbitration is lost when another device on the bus pulls this signal low. since this can occur only at the end of a serial byte, sio1 generates no further clock pulses. the synchronization logic will synchronize the serial clock generator with the clock pulses on the scl line from another device. if two or more master devices generate clock pulses, the mark duration is determined by the device that generates the shortest marks, and the space duration is determined by the device that generates the longest spaces. a slave may stretch the space duration to slow down the bus master. the space duration may also be stretched for handshaking purposes. this can be done after each bit or after a complete byte transfer. sio1 will stretch the scl space duration after a byte has been transmitted or received and the acknowledge bit has been transferred. the serial interrupt flag (si) is set, and the stretching continues until the serial interrupt flag is cleared. this block also controls all of the signals for serial byte handling. it provides the shift pulses for s1dat, enables the comparator, generates and detects start and stop conditions, receives and transmits acknowledge bits, controls the master and slave modes, contains interrupt request logic and monitors the i 2 c-bus status. 6.8.6.3 bus clock generator this programmable clock pulse generator provides the scl clock pulses when sio1 is in the master transmitter or master receiver mode. it is switched off when sio1 is in a slave mode. the output frequency is dependent on the cr bits in the control register. the output clock pulses have a 50% duty cycle unless the clock generator is synchronized with other scl clock sources as described above. 6.8.6.4 address register (s1adr) and comparator this 8-bit sfr may be loaded with the 7-bit slave address to which sio1 will respond when programmed as a slave. the least significant bit is used to enable the general call address recognition. the comparator compares the received 7-bit slave address with its own slave address. it also compares the first received byte with the general call address. if an equality is found, the appropriate status bits are set and an interrupt is requested. 6.8.6.5 data shift register (s1dat) this 8-bit sfr contains a byte of serial data to be transmitted or a byte which has just been received. data in s1dat is always shifted from right to left; the first bit to be transmitted is the msb (bit 7) and, after a byte has been received, the first bit of received data is located at the msb of s1dat. while data is being shifted out, data on the bus is simultaneously being shifted in; s1dat always contains the last byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in s1dat.
2001 jun 19 54 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.8.6.6 serial control register (s1con) this 8-bit sfr is used by the microcontroller to control the generation of start and stop conditions, enable the interface, control the generation of acks, and to select the clock frequency. 6.8.6.7 serial status register (s1sta) the status decoder takes all of the internal status bits and compresses them into a 5-bit code. this code is unique for each i 2 c-bus status. the 5-bit code may be used to generate vector addresses for fast processing of the various service routines. each service routine processes a particular bus status. there are 26 possible bus states if all four modes of sio1 are used. the 5-bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set (by hardware) and remains stable until the interrupt flag is cleared by software. the three least significant bits of the serial status register are always zero. if the status code is used as a vector to service routines, then the routines are displaced by eight address locations. eight bytes of code should be sufficient for most of the service routines. handbook, full pagewidth mbc749 - 1 slave address s1adr gc shift register s1dat sda arbitration logic scl bus clock generator s1sta internal bus 76543210 s1con 76543210 fig.24 block diagram of i 2 c-bus serial i/o.
2001 jun 19 55 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.9 msk modem the msk modem is used for in-band signalling between handset and base in analog cordless telephone systems ct0, ct1 and ct1+. the msk modems receiver and transmitter can be enabled separately. receive and transmit interrupts can wake-up the microcontroller during its power saving idle mode. baud rates are programmable. figure 25 shows the functional diagram of the msk modem. the modem has the following features: full-duplex operation via an 8-bit parallel interface the message is fully manchester coded/decoded automatic detection of 16-bit manchester preamble pattern the last received 4 bits of the preamble pattern are software programmable receiver full, transmitter empty indication bits manchester coding and decoding for clock recovery and early error detection programmable input polarity (see wdcon sfr; section 6.7.1) baud rate selection of 1 / 2976 f per , 2 / 2976 f per , 3 / 2976 f per and 4 / 2976 f per receiver and transmitter off states with no power consumption. mgu221 80c51 core mstat mcon receiver transmitter timer mbuf msk modem telx microcontroller mren mpr mten mb1,2 mclk py.y (1) px.x (1) mri mti ibd (7-0) an (7-0) r0 mout0 r1 mout1 r2 mout2 rf slicer rf vout mouthpiece tx_mute rx_mute earpiece min fig.25 msk modem functional diagram. (1) the signals rx_mute and tx_mute are handled by software. any available output pin can be used.
2001 jun 19 56 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.9.1 80c51 microcontroller interface the msk modem block interfaces to the microcontroller via the interrupt signals mri and mti and via the control and data sfrs mcon, mstat and mbuf. the msk modem receive and transmit registers are both accessed via the special function register mbuf. writing to mbuf loads the transmit register and reading mbuf accesses a physically separate receive register. table 68 msk modem related sfrs 6.9.1.1 msk modem control register (mcon) table 69 msk modem control register (sfr address d3h) table 70 description of mcon bits note 1. if both the transmitter and the receiver are disabled (mten = 0 and mren = 0), the clock of the msk modem is switched off. it is advised to use this state for power saving. table 71 selection of the modems baud rates sfr description sfr address reset value mcon msk modem control register d3h 0000 0000 mstat msk modem status register d2h xx00 0000 mbuf msk modem data buffer d1h 0000 0000 76543210 mpr3 mpr2 mpr1 mpr0 mb1 mb0 mten mren bit symbol description 7 mpr3 modem preamble pattern. these 4 bits define the modems preamble pattern. 6 mpr2 5 mpr1 4 mpr0 3 mb1 modem transmit/receive frequency. these 2 bits define the modem transmit/receive frequency; see table 71. 2 mb0 1 mten modem transmitter enable. if this bit is set the transmitter is active and mout[2:0] will get the value 100 if no data is transmitted. if reset, mout[2:0] will get the value 111 to zero the currents in the resistive dac; see note 1. 0 mren modem receiver enable. if this bit is set the modem receiver is active and scans for manchester data; see note 1. mb1 mb0 modem baud rate 00 1 / 2976 f per 01 2 / 2976 f per 10 3 / 2976 f per 11 4 / 2976 f per
2001 jun 19 57 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.9.1.2 msk modem status register (mstat) table 72 msk modem status register (sfr address d2h) table 73 description of mstat bits 6.9.1.3 msk modem data buffer (mbuf) table 74 msk modem data buffer (sfr address d1h) table 75 description of mbuf bits 76543210 -- mrf mre mrp mrl mti mri bit symbol description 5 mrf modem receiver full ?ag. mrf is set when mbuf holds a newly received byte. mrf is reset if the receiver is disabled (mren = 0) or by clearing mri. this bit is read-only; writing to it will have no effect. 4 mre modem receiver error ?ag. indicates the reception of a non-manchester bit. this bit is set by hardware and is reset by disabling the receiver (mren = 0) or by clearing mri. this bit is read-only; writing to it will have no effect. 3 mrp modem receiver preamble ?ag. mrp is set by hardware when the modem recognizes the programmed preamble pattern (aaah) after locking the receiver clock (mrl = 1). mrp is reset by hardware if the receiver is disabled (mren = 0) or if non-manchester data is received (mre = 1). this bit is read-only; writing to it will have no effect. 2 mrl modem receiver clock locked ?ag. this bit is set when the clock of the receiver is locked, i.e. when the receiver has detected three consecutive manchester bits but has not found the preamble pattern yet. mrl is reset when the receiver detects a non-manchester bit or when the receiver is disabled. this bit is read-only; writing to it will have no effect. 1 mti modem transmit interrupt ?ag. indicates mbuf is empty and ready to accept a new byte for transmission. mti is reset by writing a logic 0 to it. writing a logic 1 to mti sets the bit and allows a hardware interrupt to be generated by software. 0 mri modem receive interrupt ?ag. indicates: modem receiver full (mrf = 1) or modem receiver error (mre = 1) or modem receiver preamble (mrp = 1) or modem receiver clock locked (mrl = 1). this bit is reset by writing a logic 0 to mri. a reset of mri will also reset mre. writing a logic 1 to mri will have no effect. 76543210 d7 d6 d5 d4 d3 d2 d1 d0 bit symbol description 7 to 0 d7 to d0 writing to mbuf loads the data into the transmit buffer and starts a transmission at mout if the transmitter is enabled (mten = 1). a new byte can be loaded after mti is set. if a new byte is loaded before mti is set the previous byte will be lost. after data has been received at min, indicated by mri, the received byte can be read from mbuf.
2001 jun 19 58 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.9.2 m odem interface the modem block has the following modem interface signals, min: msk manchester coded input signal from the data slicer mout0 to mout2: 3-bit manchester coded output signal of the modem. the msk receiver input can be inverted by programming bit mskpol (wdcon.2; see section 6.7.1): mskpol = 0: direct connection between the min pin and msk receiver mskpol = 1: inverted connection between the min pin and msk receiver. the mute signals rx_mute and tx_mute must be handled by software according to the progress in the data transfer. any standard i/o port pin can be used for this purpose. 6.9.3 s ynchronisation when enabled the receiver samples min with a frequency f sample =8 baud rate. the sampled values are shifted into an 8-bit shift register. this register is regularly checked to determine whether it contains samples that fulfil the manchester coding rule, i.e. whether there is a low-to-high or a high-to-low transition in the middle of the bitcell. figure 26a shows a regular, full synchronized bitcell. figure 26b shows a regular, not synchronized bitcell, this phase shift will be corrected in the next received bitcell. figure 26c (data is faster than internal timebase) and fig.26d (data is slower than internal timebase) represent a non-valid, not synchronized bitcell. in the next received bitcell the data will be re-synchronized but the current data bit does not fulfil the manchester coding rule and will be lost. the receiver searches for three consecutive sets of 8 samples that fulfil the manchester coding rule. if these three sets have been found the clock is locked (mrl = 1) and the receiver starts looking for the manchester preamble pattern. from this point on the receiver uses a phase-locked loop (pll) to adjust the synchronisation after each received manchester bit. to detect a sample shift the receiver uses all 8 samples. if the data is at maximum, one sample out of phase, the receiver is able to resynchronize without losing data. if the data is up to three samples out of phase the receiver can still resynchronize but the data is lost. the correction is done by shifting only one sample per bitcell. this means up to three bit cells are needed for full resynchronisation. if the receiver is not able to establish resynchronization within three bitcells the lock bit (mrl) will be reset. therefore the msk modem can receive correct input data with maximum jitter of 1/f sample . mgt299 min 12345678 (a) 12345678 (c) 12345678 (d) 12345678 (b) min min min fig.26 schematic representation of a bitcell.
2001 jun 19 59 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.9.4 d ata reception a message is received as a block of one or more data bytes. when enabled, the receiver starts sampling min and tries to detect a manchester pattern. as soon as 3 consecutive manchester bits are detected the receiver clock is locked (mrl = 1) and the receiver starts scanning the incoming data for the programmed manchester preamble pattern. when the modem recognizes the preamble pattern, bit mrp is set to a logic 1. if a non-manchester bit is detected before finding the preamble pattern then mrl is reset and mre is set to a logic 1. the synchronisation process has to restart. if the preamble pattern has been detected the receiver starts to manchester decode the incoming data bits and shifts them into an internal register. after 8 bits the contents of the internal register are copied to mbuf and the mrf bit is set to a logic 1. the received byte can be read from mbuf while receiving continues in the internal register. if a non-manchester bit is received during data reception then mre is set to a logic 1 and mrl and mrp are reset. the receiver has to resynchronize before receiving new data. whenever one of the bits mrf, mre, mrp and mrl is set the mri bit is also set and a msk receive interrupt is generated. this means that when a msk receive interrupt occurs the 4 status bits have to be polled by software. the bit mrl allows the software to decide very quickly whether an occupied channel contains manchester coded data or not. the mrp bit is used to find the start of data transmission in a message that is repeated over and over again. mre is used to detect a manchester error, which is a violation of the manchester coding rule that the received level should change in the middle of a bitcell. the mrf bit indicates that the data in mbuf is ready to be read by the software. during data reception the minimum time between two settings of mrf (each one generating an mri interrupt) is: figure 27 shows an example of the data reception timing diagram. t min 8 baud rate ------------------------ - = mgu222 min data 37 no manchester code: speech?? no manchester code: speech?? data aa data ad data 1f data 37 80c51 access mri mrl mrp mre mrf write mren = 1 clear rti clear rti clear rti read mbuf 1f read mbuf 37 rx_mute should be generated by microcontroller upon interrupt rx_mute should be cleared by microcontroller at end of message fig.27 data reception timing diagram.
2001 jun 19 60 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.9.5 d ata transmission data transmission is enabled if bit mten in register mcon is set to a logic 1. if mten is a logic 0, data transmission is disabled and mout[2:0] is set to 111 to zero the currents in the resistive dac. setting mten to a logic 1 sets mout[2:0] to the idle value 100. this results in a value close to 1 / 2 v dd on the output signal of the external dac. transmission is started by loading the first byte into register mbuf. all bytes are transmitted starting with the msb. a message is transferred in a block of 3 or more bytes, the first two bytes being the programmed manchester preamble pattern. in order to insert the preamble pattern, the first two bytes aah and axh (with x being the mpr3 to mpr0 value programmed in the receiver msk modem) have to be written to mbuf by software. after this, the first byte of the message is written to mbuf. as soon as mbuf is ready to accept new input, signal mti is set. the minimum time between two mti interrupts is: if no new byte is written to mbuf at the end of a byte transmission, the modem transmitter stops transmission and mout[2:0] is set to the idle state 100. mti must be cleared explicitly. if mten is reset during transmission, the transmitter will finish the transmission of the current byte and then will set mout[2:0] to the off state 111. no interrupt on mti will be generated at the end of the transmission. t min 8 baud rate ------------------------ - = handbook, full pagewidth mgk229 mout 80c51 access set mten clear mti write mbuf aah write mbuf adh write mbuf aah write mbuf 55h write mbuf 55h mti tx_mute data adh data aah data aah data 55h data 55h fig.28 data transmission timing diagram.
2001 jun 19 61 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.9.6 w aveform generation with mout[2:0] the 3 digital output pins mout0 to mout2, should be used as an input to a 3-bit external dac. the signals can be connected via external resistors r0, r1 and r2 to a summation point and then be filtered with an external capacitor (c1). the 3-bit dac is shown in fig.29. table 76 gives the relationship between the mout pins and vout. figure 30 shows the waveforms that are produced by the waveform generator. the horizontal axis shows the sample counter on which the waveform changes its value. each bit is built-up out of 2 124 samples. the vertical axis shows the values of mout[2:0], forming the inputs of the resistive dac. the first half of the waveform is determined by the previous and the current bit, whereas the second half of the waveform is determined by the current and the next bit to be transmitted. the count frequency of the sample counter depends on the programmed baud rate. if the transmitter is disabled with mten set to a logic 0, mout[2:0] is 111 to save power in the resistive dac. if the transmitter is enabled and no data is transmitted, mout[2:0] has an idle value of 100, which corresponds to 0.57v dd . table 76 vout as a function of mout[2:0] note 1. vout with resistor values (see fig.29): r1 = 0.5r0; r2 = 0.25r0 6.9.7 m anchester coding of data the bits of the data byte written in mbuf are manchester encoded as shown in fig.30. a logic 1 is coded as a low-to-high transition in the middle of a bitcell, a logic 0 is coded as a high-to-low transition.the manchester encoded signal contains redundancy for early error detection in received bits. a non-matching high-to-low or low-to-high pair indicates an error condition.the manchester encoded signal has a polarity change in each bitcell. mout2 mout1 mout0 vout (1) 0000 0 0 1 0.14v dd 0 1 0 0.29v dd 0 1 1 0.43v dd 1 0 0 0.57v dd 1 0 1 0.71v dd 1 1 0 0.86v dd 111v dd handbook, halfpage mgk231 waveform generator mout0 mout1 mout2 r0 r1 r2 vout c1 = 10 nf fig.29 3-bit dac with mout[2:0].
2001 jun 19 62 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 handbook, full pagewidth mgk232 111 11 24 41 84 100 124 113 24 41 84 100 124 113 11 110 101 011 000 001 010 100 000 111 11 24 41 84 100 124 113 23 48 81 124 110 101 011 000 001 010 100 001 23 48 81 111 11 24 41 84 100 124 113 124 110 101 011 000 001 010 100 110 24 41 84 100 113 11 111 43 76 101 124 124 110 101 011 000 001 010 100 100 24 41 84 100 113 11 111 43 76 101 124 124 110 101 011 000 001 010 100 011 23 48 81 111 43 76 101 124 124 110 101 011 000 001 010 100 010 23 48 81 111 43 76 101 124 124 110 101 011 000 001 010 100 101 111 11 24 41 84 100 124 113 24 41 84 100 124 113 11 110 101 011 000 001 010 100 111 fig.30 waveforms with mout[2:0] for previous, current and next bits to be transmitted.
2001 jun 19 63 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.10 internal data memory internal data memory is mapped in fig.31. the memory space is divided into three blocks, which are referred to as the lower 128, the upper 128, and sfr space. internal data memory addresses are always one byte wide, which implies an address space of only 256 bytes. however, the addressing modes for internal ram can in fact accommodate 384 bytes, using a simple trick. direct addresses higher than 7fh access one memory space, and indirect addresses higher than 7fh access a different memory space. thus fig.31 shows the upper 128 and sfr space occupying the same block of addresses, 80h through ffh, although they are physically separate entities. the lower 128 bytes of ram are present in all 80c51 devices as mapped in fig.32. the lowest 32 bytes are grouped into 4 banks of 8 registers. program instructions call out these registers as r0 through r7. two bits in the program status word (psw) select which register bank is in use. this allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing. the next 16 bytes above the register banks form a block of bit-addressable memory space. the 80c51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. the bit addresses in this area are 00h through 7fh. all of the bytes in the lower 128 can be accessed by either direct or indirect addressing. the upper address space of 128 bytes is overlaid with the 128-byte sfr address space. when using indirect addressing the internal data memory is accessed but when using direct addressing the sfr memory space is accessed. figure 31 shows the overlay of internal data memory and sfr memory space. sfrs include the port latches, timers, peripheral controls, etc. sixteen addresses in sfr space are both byte-and bit-addressable. the bit-addressable sfrs are those whose address ends in 0h or 8h. mbl261 accessible by indirect addressing only upper 128 lower 128 accessible by direct and indirect addressing sfr memory space ports, status and control bits, timers, registers, stack pointer, accumulator, etc. ffh 7fh 0 80h ffh 80h accessible by direct addressing ram data memory in the 83cl882 only 128 bytes of ram are implemented, therefore the upper 128 bytes are mapped to the lower memory block fig.31 internal data memory. mgt303 00 bank select bits in psw 07h 0 01 0fh 08h 10 17h 10h 11 1fh 18h 2fh 20h 7fh bit-addressable space (bit addresses 0 to 7fh) 4 banks of 8 registers r0 to r7 reset value of stack pointer fig.32 the lower 128 bytes of internal data memory.
2001 jun 19 64 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 6.11 special function registers overview table 77 sfrs overview an empty ?eld ( - ) indicates a bit that can be read or written to by software. addr (hex) r/w bit addressable name 7 6 5 4 3 2 1 0 reset value 80 rw yes p0 --- - - - - - efh 81 rw - sp --- - - - - - 07h 82 rw - dpl --- - - - - - 00h 83 rw - dph --- - - - - - 00h 87 rw - pcon --- - - - pd idl 00h 88 rw yes tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h 89 rw - tmod gate c/ tm1 m0 gate c/ t m1 m0 00h 8a rw - tl0 --- - - - - - 00h 8b rw - tl1 --- - - - - - 00h 8c rw - th0 --- - - - - - 00h 8d rw - th1 --- - - - - - 00h 8e rw - p0cfga --- - - - - - f3h 8f rw - p0cfgb --- - - - - - 00h 90 rw yes p1 --- - - - - - ffh 9e rw - p1cfga --- - - - - - ffh 9f rw - p1cfgb --- - - - - - 00h a5 rw - wdcon cond wd3 wd2 wd1 wd0 mskpol - ld 00h a6 rw - wdtim --- - - - - - 00h a8 rw yes ien0/ie ea et2 es1 - et1 ex1 et0 ex0 00h b0 rw yes p3 --- - - - - - ffh b4 rw - syscon t1src1 t1src0 t0src1 t0src0 -- select xtm 00h b8 rw yes ip0 - pt2 ps1 - pt1 px1 pt0 px0 00h be rw - p3cfga --- - - - - - ffh bf rw - p3cfgb --- - - - - - 00h c0 rw yes irq1 iq9 iq8 iq7 iq6 iq5 iq4 iq3 iq2 00h c8 rw yes t2con t2f exf2 -- exen2 tr2 c/ t2 cp/ rl2 00h c9 rw - t2mod --- - - t2rd c/t2oe cp/dcen 00h ca rw - t2rcl --- - - - - - 00h
2001 jun 19 65 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 notes 1. this bit is read only. 2. this bit is set to logic 1 by hardware; can only be cleared by software. cb rw - t2rch --- - - - - - 00h cc rw - t2l --- - - - - - 00h cd rw - t2h --- - - - - - 00h d0 rw yes psw cy ac f0 rs1 rs0 ov - p (1) 00h d1 rw - mbuf d7 d6 d5 d4 d3 d2 d1 d0 00h d2 rw - mstat -- mrf (1) mre (1) mrp (1) mrl (1) mti mri (2) 00h d3 rw - mcon mpr3 mpr2 mpr1 mpr0 mb1 mb0 mten mren 00h d8 rw yes s1con cr2 ens1 sta sto si aa cr1 cr0 00h d9 r - s1sta sc4 sc3 sc2 sc1 sc0 0 0 0 f8h da rw - s1dat --- - - - - - 00h db rw - s1adr sla6 sla5 sla4 sla3 sla2 sla1 sla0 gc 00h dd rw - wkcon --- - - - - - 00h e0 rw yes acc --- - - - - - 00h e1 rw - ise1 ise9 ise8 ise7 ise6 ise5 ise4 ise3 ise2 00h e8 rw yes ien1 ex9 ex8 ex7 ex6 ex5 ex4 ex3 ex2 00h e9 rw - ix1 ix9 ix8 ix7 ix6 ix5 ix4 ix3 ix2 00h f0 rw yes b --- - - - - - 00h f1 rw - ien2 ewdi eadi ekpi - elvd - emti emri 00h f3 rw - presc extck auxsw sync ----- 00h f8 rw yes ip1 px7 px6 px5 px6 px5 px4 px3 px2 00h f9 rw - ip2 pwdi padi pkpi - plvd - pmti pmri 00h addr (hex) r/w bit addressable name 7 6 5 4 3 2 1 0 reset value
2001 jun 19 66 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 7 instruction set the asynchronous 80c51 family uses a powerful instruction set which permits the expansion of on-chip cpu peripherals and optimizes power consumption in idle and active modes as well as byte efficiency and execution speed. typical execution times and energy consumption at room temperature (t amb =25 c) and v dd = 3.0 v are given in table 78. remark: for most opcodes the numbers for execution speed and energy are also strongly dependent on the data (add, subb, dec, inc, mul, div, da conditional jumps etc.) and the operand address (cpu internal sfrs or sfrs in a peripheral block). table 78 instruction set mnemonic description bytes exec. time (1) ( m s) energy (1) (nj) opcode (hex) arithmetic operations add a, rn add register to a 1 0.20 1.13 2* add a, direct add direct byte to a 2 0.24 1.68 25 add a, @ ri add indirect ram to a 1 0.21 1.36 26 and 27 add a, #data add immediate data to a 2 0.23 1.40 24 addc a, rn add register to a with carry ?ag 1 0.20 1.14 3* addc a, direct add direct byte to a with carry ?ag 2 0.25 1.68 35 addc a, @ri add indirect ram to a with carry ?ag 1 0.21 1.37 36 and 37 addc a, #data add immediate data to a with carry ?ag 2 0.23 1.45 34 subb a, rn subtract register from a with borrow 1 0.20 1.13 9* subb a, direct subtract direct byte from a with borrow 2 0.24 1.69 95 subb a, @ri subtract indirect ram from a with borrow 1 0.21 1.36 96 and 97 subb a, #data subtract immediate data from a with borrow 2 0.23 1.43 94 inc a increment a 1 0.17 0.79 04 inc rn increment register 1 0.18 1.16 0* inc direct increment direct byte 2 0.22 1.75 05 inc @ri increment indirect ram 1 0.19 1.35 06 and 07 dec a decrement a 1 0.17 0.81 14 dec rn decrement register 1 0.18 1.17 1* dec direct decrement direct byte 2 0.22 1.75 15 dec @ri decrement indirect ram 1 0.19 1.38 16 and 17 inc dptr increment data pointer 1 0.15 0.78 a3 mul ab multiply a and b 1 0.15 0.70 a4 div ab divide a by b 1 0.73 3.58 84 da a decimal adjust a 1 0.17 0.74 d4 logic operations anl a, rn and register to a 1 0.20 1.24 5* anl a, direct and direct byte to a 2 0.30 1.91 55 anl a, @ri and indirect ram to a 1 0.21 1.44 56 and 57 anl a, #data and immediate data to a 2 0.23 1.50 54
2001 jun 19 67 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 anl direct, a and a to direct byte 2 0.26 1.96 52 anl direct, #data and immediate data to direct byte 3 0.28 2.41 53 orl a, rn or register to a 1 0.29 1.71 4* orl a, direct or direct byte to a 2 0.29 1.72 45 orl a, @ri or indirect ram to a 1 0.19 1.27 46 and 47 orl a, #data or immediate data to a 2 0.21 1.23 44 orl direct, a or a to direct byte 2 0.24 1.78 42 orl direct, #data or immediate data to direct byte 3 0.27 2.16 43 xrl a, rn exclusive-or register to a 1 0.29 1.72 6* xrl a, direct exclusive-or direct byte to a 2 0.29 1.72 65 xrl a, @ri exclusive-or indirect ram to a 1 0.19 1.31 66 and 67 xrl a, #data exclusive-or immediate data to a 2 0.21 1.33 64 xrl direct, a exclusive-or a to direct byte 2 0.24 1.83 62 xrl direct, #data exclusive-or immediate data to direct byte 3 0.27 2.27 63 clr a clear a 1 0.14 0.71 e4 cpl a complement a 1 0.15 0.93 f4 rl a rotate a left 1 0.15 0.73 23 rlc a rotate a left through the carry ?ag 1 0.15 0.74 33 rr a rotate a right 1 0.17 0.82 03 rrc a rotate a right through the carry ?ag 1 0.15 0.73 13 swap a swap nibbles within a 1 0.14 0.71 c4 data transfer mov a, rn move register to a 1 0.15 0.89 e* mov a, direct move direct byte to a 2 0.19 1.49 e5 mov a, @ri move indirect ram to a 1 0.16 1.13 e6 and e7 mov a, #data move immediate data to a 2 0.21 1.85 74 mov rn, a move a to register 1 0.13 0.86 f* mov rn, direct move direct byte to register 2 0.23 1.90 a* mov rn, #data move immediate data to register 2 0.16 1.28 7* mov direct, a move a to direct byte 2 0.18 1.47 f5 mov direct, rn move register to direct byte 2 0.21 1.68 8* mov direct, direct move direct byte to direct byte 3 0.25 2.22 85 mov direct, @ri move indirect ram to direct byte 2 0.22 1.92 86 and 87 mov direct, #data move immediate data to direct byte 3 0.21 1.85 75 mov @ri, a move a to indirect ram 1 0.14 1.01 f6 and f7 mov @ri, direct move direct byte to indirect ram 2 0.25 2.09 a6 and a7 mov @ri, #data move immediate data to indirect ram 3 0.11 0.92 76 and 77 mov dptr, #data 16 load data pointer with a 16-bit constant 3 0.20 1.58 90 mnemonic description bytes exec. time (1) ( m s) energy (1) (nj) opcode (hex)
2001 jun 19 68 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 movc a, @a + dptr move code byte relative to dptr to a 1 0.31 2.34 93 movc a, @a + pc move code byte relative to pc to a 1 0.32 2.47 83 movx (2) a, @ri move external ram (8-bit address) to a 1 -- e2 and e3 movx (2) a, @dptr move external ram (16-bit address) to a 1 -- e0 movx (2) @ri, a move a to external ram (8-bit address) 1 -- f2 and f3 movx (2) @dptr,a move a to external ram (16-bit address) 1 -- f0 push direct push direct byte onto stack 2 0.26 1.62 c0 pop direct pop direct byte from stack 2 0.26 1.66 d0 xch a, rn exchange register with a 1 0.20 1.35 c* xch a, direct exchange direct byte with a 2 0.25 1.98 c5 xch a, @ri exchange indirect ram with a 1 0.21 1.42 c6 and c7 xchd a, @ri exchange low-order nibble indirect ram with a 1 0.19 1.38 d6 and d7 boolean variable manipulation clr c clear carry ?ag 1 0.11 0.64 c3 clr bit clear direct bit 2 0.24 1.51 c2 setb c set carry ?ag 1 0.11 0.65 d3 setb bit set direct bit 2 0.24 1.71 d2 cpl c complement carry ?ag 1 0.12 0.68 b3 cpl bit complement direct bit 2 0.23 1.59 b2 anl c, bit and direct bit to carry ?ag 2 0.21 1.30 82 anl c, /bit and complement of direct bit to carry ?ag 2 0.23 1.55 b0 orl c, bit or direct bit to carry ?ag 2 0.21 1.33 72 orl c, /bit or complement of direct bit to carry ?ag 2 0.23 1.54 a0 mov c, bit move direct bit to carry ?ag 2 0.22 1.34 a2 mov bit, c move carry ?ag to direct bit 2 0.24 1.52 92 program and machine control acall addr11 absolute subroutine call 2 0.40 2.64 1 addr lcall addr16 long subroutine call 3 0.45 3.09 12 ret return from subroutine 1 0.20 1.03 22 reti return from interrupt 1 0.43 3.01 32 ajmp addr11 absolute jump 2 0.29 1.76 1 addr ljmp addr16 long jump 3 0.32 2.14 02 sjmp rel short jump (relative address) 2 0.26 1.50 80 jmp @a+dptr jump indirect relative to the dptr 1 0.46 2.63 73 jz rel jump if a is zero 2 0.29 1.62 60 jnz rel jump if a is not zero 2 0.26 1.34 70 jc rel jump if carry ?ag is set 2 0.24 1.23 40 jnc rel jump if carry ?ag is not set 2 0.29 1.61 50 mnemonic description bytes exec. time (1) ( m s) energy (1) (nj) opcode (hex)
2001 jun 19 69 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 notes 1. verified on sampling base. 2. only applicable if xram is present on-chip (no external access possible). table 79 notation for data addressing modes table 80 hexadecimal opcode cross-reference jb bit, rel jump if direct bit is set 3 0.31 1.90 20 jnb bit, rel jump if direct bit is not set 3 0.36 2.29 30 jbc bit, rel jump if direct bit is set and clear bit 3 0.36 2.25 10 cjne a, direct, rel compare direct to a and jump if not equal 3 0.34 2.27 b5 cjne a, #data, rel compare immediate to a and jump if not equal 3 0.35 2.38 b4 cjne rn, #data, rel compare immediate to register and jump if not equal 3 0.35 2.59 b* cjne ri, #data, rel compare immediate to indirect and jump if not equal 3 0.36 2.82 b6 and b7 djnz rn, rel decrement register and jump if not zero 2 0.33 2.29 d* djnz direct, rel decrement direct and jump if not zero 3 0.39 2.89 d5 nop no operation 1 0.11 0.63 00 symbol description r n working registers r0 to r7 direct 128 internal ram locations and any special function register (sfr) r i indirect internal ram location addressed by register r0 or r1 #data 8-bit constant included in instruction #data 16 16-bit constant included as bytes 2 and 3 of instruction bit direct addressed bit in internal ram or sfr addr16 16-bit destination address; used by lcall and ljmp; the branch will be anywhere within the 64 kbytes program memory address space addr11 11-bit destination address; used by acall and ajmp. the branch will be within the same 2-kbyte page of program memory as the ?rst byte of the following instruction rel signed (twos complement) 8-bit offset byte; used by sjmp and all conditional jumps; range is - 128 to +127 bytes relative to ?rst byte of the following instruction symbol description * 8,9,a,b,c,d,eandf 11, 31, 51, 71, 91, b1, d1 and f1 01, 21, 41, 61, 81, a1, c1 and e1 mnemonic description bytes exec. time (1) ( m s) energy (1) (nj) opcode (hex)
2001 jun 19 70 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 7.1 instruction map a ndbook, full pagewidth first hexadecimal character of opcode movc a,@a+dptr second hexadecimal character of opcode 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123 456 789abcdef nop jbc bit,rel jb bit,rel jnb bit,rel jc rel jnc rel jz rel jnz rel sjmp rel mov dptr,#data 16 orl c,/bit anl c,/bit push direct pop direct movx a,@dptr movx @dptr,a ajmp addr11 acall addr11 ajmp addr11 acall addr11 ajmp addr11 acall addr11 ajmp addr11 acall addr11 ajmp addr11 acall addr11 ajmp addr11 acall addr11 ajmp addr11 acall addr11 ajmp addr11 acall addr11 ljmp addr16 lcall addr16 ret reti orl direct,a anl direct,a xrl direct,a orl c,bit anl c,bit mov bit,c mov c,bit cpl bit clr bit setb bit 01 01 movx @ri,a movx a,@ri rr a rrc a rlc a orl direct,#data anl direct,#data xrl direct,#data jmp @a+dptr movc a,@a+pc inc dptr cpl c clr c setb c rl a inc a dec a add a,#data addc a,#data orl a,#data anl a,#data xrl a,#data mov a,#data div ab subb a,#data mul ab cjne a,#data,rel swap a da a clr a cpl a inc direct dec direct add a,direct addc a,direct orl a,direct anl a,direct xrl a,direct mov direct,#data mov direct,direct subb a,direct cjne a,direct,rel xch a,direct djnz direct,rel mov a,direct mov direct,a * 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 inc@ri dec@ri add a,@ri addc a,@ri orl a,@ri anl a,@ri xrl a,@ri mov @ri,#data mov direct,@ri subb a,@ri mov @ri,direct cjne @ri,#data,rel xch a,@ri xchd a,@ri mov a,@ri mov @ri,a inc rn dec rn add a,rn addc a,rn orl a,rn anl a,rn xrl a,rn mov direct,rn subb a, rn mov rn,direct cjne rn,#data,rel xch a,rn djnz rn,rel mov a,rn mov rn,a mov rn,#data * mov a, acc is not a valid instruction. mgl457 fig.33 instruction map.
2001 jun 19 71 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 8 application information 8.1 introduction this chapter presents some information about how to use the p83cl882 in an application. it is not intended to replace the application notes but serves as a quick help when starting to work with the philips ultra low power handshake microcontrollers. there are some important improvements between the silicon in plastic packages and the metalink eh emulator system which are described here. furthermore, some hints on software development and power consumption are given to help the user take advantage of the full benefits of the handshake cpu. 8.2 differences between p83cl882 and the metalink eh emulation system the syscon sfr does not exist on the emulator system on the emulator the oscillator can only be used in normal mode which is the default start-up mode of the p83cl882. the hysteresis input comparator does not exist the clock source of the timer 0 and 1 is always f psc on the emulator system. the timers can be used as counters, counting from external pin t1 or t0 but this is not possible in power-down mode. the interrupts t0 and t1 can cause on the emulator only a wake-up from idle and not from power-down prescaler bits presc[7:5] are not available on the emulator; therefore the synchronous mode and clock out functionality is not present msk polarity cannot be inverted on the emulator int1 interrupt is on the emulator version present on p3.3 where it is mapped on p3.1 on the p83cl882 the clock output on p1.4 does not exist on the emulator. 8.3 the asynchronous handshake cpu as the cpu of the p83cl882 is built in asynchronous technology (hand-shake mechanism) some properties are singular to it in comparison to standard synchronous 80c51 controllers: the cpu itself does not need a clock for code execution the performance (mips) is not dependent on oscillator frequency but strongly related to v dd , temperature, silicon parameters and type of software. it always runs at the maximum speed determined by the external influences above. therefore, it operates also with the maximum power consumption in the minimum time. generally the lower the temperature and the higher the v dd the faster the cpu runs. details on instruction speed and energy consumption per instruction can be found in chapter 7. because of the above mentioned properties some hints are given for using this controller in any kind of application in an efficient way. due to the high cpu performance, independent of clock frequency, certain functions (e.g. serial or customized interfaces) can be built in software in a very efficient and flexible way. in classic 80c51 software the user (software engineer) was able to rely on cycle-timing for wait-loops, synchronisation in the system or similar usage (e.g. nop instruction for waiting one machine cycle). when using the asynchronous cpu wait-loops should be implemented by starting a timer and putting the cpu in idle mode in order to wait for an interrupt. significant power reduction and a much more robust software will be obtained. if in an application the instruction counter is needed timer 0 or 1 can be used with the instruction request signal connected to the clock source input. one should avoid using wait-until-loops (sfr polling). this would lead to maximum cpu-load resulting in very high current consumption. the cpu should always be used as an event driven machine waiting for interrupts. after an activity the device must be entered in idle or power-down mode as fast as possible, the current is then reduced down to leakage. the device provides flexible means (interrupts, timer, counters) for a recovery from these power reduction modes.
2001 jun 19 72 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 9 how to estimate p83cl882 power consumption 9.1 general due to the use of the philips unique asynchronous technology within the cpu, the power estimation must be done by taking into account several circumstances. to have an accurate power estimation the application must be well known. this especially means that all (or the most significant) application modes (e.g. idle or operation modes) are known and their weight or contribution C what is done when with which occurrence C can be estimated precise enough. 9.2 modes 9.2.1 p ower - down mode in power-down there is no circuitry active which is drawing current. the cpu, the oscillator, the clock tree and the peripheral functions are switched off except timer 0 and 1 which can function as counter in power-down mode. the device can be woken-up by an interrupt. in this mode the power consumption is only dependent on outside activity (port toggling, gate-current) and leakage (see fig.34). 9.2.2 i dle mode in idle mode the oscillator (if enabled), the clock tree and the enabled peripheral functions are running. the peripheral functions are fixed to the peripheral clock (f per or f psc ). in figs 39, 39 and 39 one can see the behaviour of the idle current with no peripheral functions switched on. 9.2.3 o perating mode in operating mode the cpu, the oscillator, the clock tree and the enabled peripheral functions are running. while the peripheral functions are fixed to the peripheral clock (f per or f psc ) the cpu is completely free running. in plain words: it does one instruction after the other without any clocking nor timing scheme. in addition to that and to make code execution faster following instruction is pre-fetched while an instruction is being executed. 9.3 examples of power consumption estimation a rough estimation of device power consumption can be made by an add-up of the power-down mode current, idle mode current, enabled peripheral function(s) current and estimated cpu processing load times mean value of operating current: i dd(pd) +i dd(id) +i periphery + cpu load i dd(op) . assume an application part where the device is 50% in idle, during idle for total 40% a peripheral function is running, for 20% the cpu is active and the rest is power-down state. then the averaged power consumption can roughly be calculated as follows: i average = (100% i dd(pd) ) + (50% i dd(id) ) + (40% i periphery ) + (20% i dd(op) ). when the number of instructions within an application part and its execution time is known, then the cpu processing load can be estimated as shown below. the cpu performance (in mips) is given by the supply voltage: cpu processing load 100% number of instructions time (seconds) ---------------------------------------------------------- - 10 6 C cpu performance (in mips) ------------------------------------------------------------------------ =
2001 jun 19 73 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 9.3.1 e xample of ring - detection typically a ring-detection is done by a time measurement using a timer. the device is activated by an external interrupt (e.g. ac on the a/b line), the oscillator runs up and the device carries out the time measurement with a timer. in this example it can be assumed that to read the timer contents, decide whether an external ringer should be enabled or not, to restart the timer and then go into idle mode is around 30 instructions. assuming a ringing frequency of about 25 hz and a device supply voltage of 3.0 v this gives a cpu performance of about 4.5 mips. the cpu processing load is then: from the calculation above it can be seen that the idle current will be dominant in this application part. 100% 30 instructions 25 hz 4.5 mips 1000000 --------------------------------------------------------------------------------- - 0.017% ? mgt314 a/b line activity cpu operation idle idle idle idle idle idle fig.34 ring-detection sequence.
2001 jun 19 74 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 10 limiting values according to the absolute maximum ratings system (iec 60134); note 1. notes 1. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise specified. 2. may not exceed the limiting value for v dd . 3. according to snw-fq-302a: c = 100 pf; r = 1.5 kw. 4. according to snw-fq-302b: c = 200 pf; l = 0.75 mh. symbol parameter conditions min. max. unit v dd supply voltage - 0.5 +4.6 v v i input voltage note 2 - 0.5 v dd + 0.5 v i i/o maximum sink/source current for each input/output pin - 10 ma i dd maximum supply current for any supply pin - 50 ma v es electrostatic handling voltage human body model; note 3 - 2000 v machine model; note 4 - 175 v p tot total power dissipation - 100 mw t stg storage temperature - 55 +125 c t amb operating ambient temperature (for all devices) - 25 +70 c
2001 jun 19 75 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 11 characteristics v dd = 1.8 to 3.6 v; v ss =0v; f xtal = 4 mhz; t amb = - 25 to +70 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. (1) unit supply v dd supply voltage operating 1.8 (2) - 3.6 v ram data retention 1.0 - 3.6 v i dd operating supply current v dd =3v; t amb =25 c; at 100% cpu load note 3 -- 4.5 ma notes 4 and 5 - 3.0 - ma i dd(id) supply current idle mode v dd = 3 v; external clock; note 6 - 60 75 m a v dd =3v; t amb =25 c; crystal connected; note 5 - 300 -m a i dd(pd) supply current power-down mode v dd =3v; t amb =25 c; note 7 - 0.1 -m a v dd =3v; t amb =70 c; note 7 -- 4.5 m a i dd(block) supply current per block: v dd =3v; t amb =25 c; note 8 msk modem - 14 -m a watchdog timer - 2 -m a i 2 c-bus - 30 -m a timer 2 - 4 -m a timer 0 or 1 - 10 -m a performance f xtal1 external clock input frequency notes 5 and 9 dc - 12 mhz cpu perf cpu performance t amb =25 c; notes 4 and 5 v dd = 1.8 v - 2.6 - mips v dd = 3.0 v - 4.5 - mips cpu eff cpu ef?ciency t amb =25 c; notes 4 and 5 v dd = 1.8 v - 1910 - mips/w v dd = 3.0 v - 555 - mips/w
2001 jun 19 76 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 inputs (ports, min and rst) v il low-level input voltage notes 10 and 11 0 - 0.2v dd v v ih high-level input voltage note 10 0.8v dd - v dd v ? i il ? low-level input current; ports in standard port con?guration v in = 0.4 v; note 12; see fig.44 - 20 50 m a ? i il(t) ? low-level input current; high-to-low transition; ports in standard port con?guration v in = 0.5v dd ; note 12; see fig.44 - 200 1000 m a ? i li ? input leakage current; ports in open-drain or high-impedance input con?guration v ss v i v dd -- 100 na outputs (ports and rst) i ol low-level output current; except sda and scl; note 12 v dd = 3.0 v; v ol = 0.4 v 4 -- ma v dd = 3.0 v; v ol = 1.5 v - 10 - ma i oh high -level output current; push-pull con?guration only v dd =3v; v oh =v dd - 0.4 v 4 -- ma v dd =3v; v oh =v dd - 1.5 v - 10 - ma i rst rst pull-up resistor current v dd =3v; v oh =v dd - 0.4 v 0.05 0.1 -m a v dd =3v; v oh =v ss - 0.3 2.5 m a amplitude controlled oscillator (aco) f osc oscillator frequency notes 5 and 9 1 - 12 mhz r fb feedback resistance note 5 - 200 - k w g m transconductance t amb =25 c; v dd = 1.8 v 1.0 - 2.5 ms t amb =25 c; v dd = 3 v 3.0 - 6ms c i(l)(xtal1) capacitive input load on xtal1 - 500 1000 ff v xtal1(p-p) external clock signal amplitude on pin xtal1 (peak-to-peak value) in oscillator mode 0.4v dd - v dd v v dc(xtal1) mean value of external clock signal in oscillator mode - 0.5v dd - v v il(xtal1) low-level input voltage pin xtal1 in external clock mode 0 - 0.2v dd v v ih(xtal1) high-level input voltage pin xtal1 in external clock mode 0.6v dd - v dd v c 1e ,c 2e external required load capacitance on xtal1 and xtal2 - 22 - pf symbol parameter conditions min. typ. max. (1) unit
2001 jun 19 77 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 notes 1. the measurement of the maximum value is done with all output pins disconnected; v il =v ss ;v ih =v dd ; rst=v dd ; xtal1 driven with square wave; xtal2 not connected; all derivative blocks disabled. to see the typical value of each instruction please consult table 78 instruction set. 2. the minimum operating voltage is the level where vdd is higher than the power-on reset level. 3. for this measurement an instruction was selected which current consumption is around the typical value; the instruction is: ljmp to addr + 03h. 4. the typical operating supply current is evaluated as a mean value over all possible instructions (100% cpu load) and with a crystal connected. 5. verified on sampling basis. 6. the idle mode supply current is measured with all output pins and rst disconnected; v il =v ss ; v ih =v dd ; xtal1 driven with square wave; xtal2 not connected; all derivative blocks disabled. 7. the power-down mode supply current is measured with all output pins and rst disconnected; v il =v ss ;v ih =v dd ; xtal1 and xtal2 not connected. 8. the typical currents are only for the specific block. to calculate the typical power consumption of the microcontroller, the current consumption of the cpu weighted with the processing must be added. example: the typical average current consumption of the microcontroller in operating mode with 10% cpu processing load, watchdog timer and msk active can be calculated as: 10% i cpu +i dd(id) +i wd +i msk . 9. for some peripheral blocks it could be required to reduce the internal clock frequency with the psc2 and an additional divider inside the peripherals. symbol f xtal1 is meant for external device clocking and f osc is meant as on-chip oscillator frequency. 10. the input threshold voltage of p1.6/scl and p1.7/sda meet the i 2 c-bus specification. therefore, an input voltage below 0.3v dd will be recognized as a logic 0 and an input voltage above 0.7v dd will be recognized as a logic 1. 11. not valid for pins sda, scl, rst and min. 12. due to the maximum allowed current, the number of output pins switching at the same time should be limited to one.
2001 jun 19 78 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 handbook, halfpage 1.5 5 mips 0 1 mgw040 2 4 3 2 2.5 3 3.5 4 v dd (v) fig.35 typical cpu performance as a function of v dd , t amb =25 c (mean value over all instructions). handbook, halfpage - 50 100 5 mips 0 1 mgw041 2 3 4 - 250 255075 t amb ( c) fig.36 typical cpu performance as a function of t amb , v dd = 3 v (mean value over all instructions). handbook, halfpage 1.5 2000 mips/w 0 400 mgw042 800 1600 1200 2 2.5 3 3.5 4 v dd (v) fig.37 typical cpu efficiency as a function of v dd , t amb =25 c (mean value over all instructions). handbook, halfpage 1.5 5 i dd (ma) 0 1 mgw043 2 4 3 2 2.5 3 3.5 4 v dd (v) fig.38 typical operating current as a function of v dd , t amb =25 c; 100% cpu load (mean value over all instructions).
2001 jun 19 79 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 handbook, halfpage - 50 100 4 i dd (ma) 0 1 mgw044 2 3 - 250 255075 t amb ( c) fig.39 typical operating current as a function of t amb , v dd = 3.0 v; 100% cpu load (mean value over all instructions). handbook, halfpage 1.5 i dd ( m a) 0 100 mgw045 200 400 300 2 2.5 3 3.5 4 v dd (v) fig.40 typical idle current as a function of v dd , t amb =25 c; f osc = 4 mhz (crystal). handbook, halfpage - 50 100 400 i dd ( m a) 0 100 mgw046 200 300 - 250 255075 t amb ( c) fig.41 typical idle current as a function of t amb , v dd = 3.0 v; f osc = 4 mhz (crystal). handbook, halfpage 0 i dd ( m a) 0 100 mgw047 200 400 300 246 10 812 f osc (mhz) fig.42 typical idle current as a function of oscillator (crystal) frequency, v dd = 3.0 v; t amb =25 c.
2001 jun 19 80 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 0 (1) (2) 12 4 4 3 i dd(pd) ( m a) 1 0 2 3 v dd (v) mbl262 fig.43 typical power-down current as a function of v dd . (1) t amb =70 c (2) t amb =25 c handbook, full pagewidth mgl506 0.5v dd 0.3v dd v dd 0 i il(t) i il i i 500 m a 10 m a fig.44 port input current.
2001 jun 19 81 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 12 package outline unit a 1 a 2 a 3 b p cd (1) e (2) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.05 0.95 0.85 0.30 0.19 0.20 0.09 11.10 10.90 6.20 6.00 0.65 8.30 7.90 0.78 0.48 8 0 o o 0.10 0.10 0.20 1.00 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot487-1 mo-153 97-06-11 99-12-27 w m b p d z e 0.25 116 32 17 q a a 1 a 2 l p detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm sot487-1 a max. 1.10 pin 1 index
2001 jun 19 82 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 13 soldering 13.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 13.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 13.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2001 jun 19 83 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 13.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
2001 jun 19 84 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 14 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. 15 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 16 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2001 jun 19 85 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 17 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2001 jun 19 86 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 notes
2001 jun 19 87 philips semiconductors product speci?cation 80c51 ultra low power (ulp) telephony controller p83cl882 notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2001 72 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, marketing communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 7 - 9 rue du mont valrien, bp317, 92156 suresnes cedex, tel. +33 1 4728 6600, fax. +33 1 4728 6638 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: philips hungary ltd., h-1119 budapest, fehervari ut 84/a, tel: +36 1 382 1700, fax: +36 1 382 1800 india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 5f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2451, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 60/14 moo 11, bangna trad road km. 3, bagna, bangkok 10260, tel. +66 2 361 7910, fax. +66 2 398 3447 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 753505/01/pp 88 date of release: 2001 jun 19 document order number: 9397 750 07598

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